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llvm-mirror/test/CodeGen/PowerPC/pr25080.ll

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[PowerPC] Fix ICE when truncating some vectors The legalizer would hit an assertion on PowerPC platform when truncating a vector whose size is not power of 2. This patch is to add a check to prevent vectors with such odd-size elements from being custom lowered. Reviewed By: Hal Finkel Differential Revision: https://reviews.llvm.org/D65261 llvm-svn: 368654
2019-08-13 09:53:29 +02:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- -mcpu=pwr8 < %s | FileCheck %s --check-prefix=LE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mcpu=pwr8 < %s | FileCheck %s --check-prefix=BE
define <8 x i16> @pr25080(<8 x i32> %a) {
; LE-LABEL: pr25080:
; LE: # %bb.0: # %entry
; LE-NEXT: addis 3, 2, .LCPI0_0@toc@ha
; LE-NEXT: xxlxor 37, 37, 37
; LE-NEXT: addi 3, 3, .LCPI0_0@toc@l
; LE-NEXT: lvx 4, 0, 3
; LE-NEXT: xxland 34, 34, 36
; LE-NEXT: xxland 35, 35, 36
; LE-NEXT: vcmpequw 2, 2, 5
; LE-NEXT: vcmpequw 3, 3, 5
; LE-NEXT: xxswapd 0, 34
; LE-NEXT: mfvsrwz 3, 34
; LE-NEXT: xxsldwi 1, 34, 34, 1
; LE-NEXT: mfvsrwz 4, 35
[PowerPC] Canonicalize shuffles to match more single-instruction masks on LE We currently miss a number of opportunities to emit single-instruction VMRG[LH][BHW] instructions for shuffles on little endian subtargets. Although this in itself is not a huge performance opportunity since loading the permute vector for a VPERM can always be pulled out of loops, producing such merge instructions is useful to downstream optimizations. Since VPERM is essentially opaque to all subsequent optimizations, we want to avoid it as much as possible. Other permute instructions have semantics that can be reasoned about much more easily in later optimizations. This patch does the following: - Canonicalize shuffles so that the first element comes from the first vector (since that's what most of the mask matching functions want) - Switch the elements that come from splat vectors so that they match the corresponding elements from the other vector (to allow for merges) - Adds debugging messages for when a shuffle is matched to a VPERM so that anyone interested in improving this further can get the info for their code Differential revision: https://reviews.llvm.org/D77448
2020-06-19 04:53:50 +02:00
; LE-NEXT: xxsldwi 2, 34, 34, 3
; LE-NEXT: mtvsrd 36, 3
[PowerPC] Ignore implicit register operands for MCInst Summary: When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands, it will expose more opportunity for InstiAlias. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77118
2020-04-16 18:22:43 +02:00
; LE-NEXT: mffprwz 3, 0
[PowerPC] Fix ICE when truncating some vectors The legalizer would hit an assertion on PowerPC platform when truncating a vector whose size is not power of 2. This patch is to add a check to prevent vectors with such odd-size elements from being custom lowered. Reviewed By: Hal Finkel Differential Revision: https://reviews.llvm.org/D65261 llvm-svn: 368654
2019-08-13 09:53:29 +02:00
; LE-NEXT: xxswapd 0, 35
[PowerPC] Canonicalize shuffles to match more single-instruction masks on LE We currently miss a number of opportunities to emit single-instruction VMRG[LH][BHW] instructions for shuffles on little endian subtargets. Although this in itself is not a huge performance opportunity since loading the permute vector for a VPERM can always be pulled out of loops, producing such merge instructions is useful to downstream optimizations. Since VPERM is essentially opaque to all subsequent optimizations, we want to avoid it as much as possible. Other permute instructions have semantics that can be reasoned about much more easily in later optimizations. This patch does the following: - Canonicalize shuffles so that the first element comes from the first vector (since that's what most of the mask matching functions want) - Switch the elements that come from splat vectors so that they match the corresponding elements from the other vector (to allow for merges) - Adds debugging messages for when a shuffle is matched to a VPERM so that anyone interested in improving this further can get the info for their code Differential revision: https://reviews.llvm.org/D77448
2020-06-19 04:53:50 +02:00
; LE-NEXT: mtvsrd 37, 4
[PowerPC] Ignore implicit register operands for MCInst Summary: When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands, it will expose more opportunity for InstiAlias. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77118
2020-04-16 18:22:43 +02:00
; LE-NEXT: mffprwz 4, 1
[PowerPC] Canonicalize shuffles to match more single-instruction masks on LE We currently miss a number of opportunities to emit single-instruction VMRG[LH][BHW] instructions for shuffles on little endian subtargets. Although this in itself is not a huge performance opportunity since loading the permute vector for a VPERM can always be pulled out of loops, producing such merge instructions is useful to downstream optimizations. Since VPERM is essentially opaque to all subsequent optimizations, we want to avoid it as much as possible. Other permute instructions have semantics that can be reasoned about much more easily in later optimizations. This patch does the following: - Canonicalize shuffles so that the first element comes from the first vector (since that's what most of the mask matching functions want) - Switch the elements that come from splat vectors so that they match the corresponding elements from the other vector (to allow for merges) - Adds debugging messages for when a shuffle is matched to a VPERM so that anyone interested in improving this further can get the info for their code Differential revision: https://reviews.llvm.org/D77448
2020-06-19 04:53:50 +02:00
; LE-NEXT: xxsldwi 1, 35, 35, 1
; LE-NEXT: mtvsrd 34, 3
; LE-NEXT: mffprwz 3, 2
; LE-NEXT: mtvsrd 32, 4
[PowerPC] Ignore implicit register operands for MCInst Summary: When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands, it will expose more opportunity for InstiAlias. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77118
2020-04-16 18:22:43 +02:00
; LE-NEXT: mffprwz 4, 0
[PowerPC] Canonicalize shuffles to match more single-instruction masks on LE We currently miss a number of opportunities to emit single-instruction VMRG[LH][BHW] instructions for shuffles on little endian subtargets. Although this in itself is not a huge performance opportunity since loading the permute vector for a VPERM can always be pulled out of loops, producing such merge instructions is useful to downstream optimizations. Since VPERM is essentially opaque to all subsequent optimizations, we want to avoid it as much as possible. Other permute instructions have semantics that can be reasoned about much more easily in later optimizations. This patch does the following: - Canonicalize shuffles so that the first element comes from the first vector (since that's what most of the mask matching functions want) - Switch the elements that come from splat vectors so that they match the corresponding elements from the other vector (to allow for merges) - Adds debugging messages for when a shuffle is matched to a VPERM so that anyone interested in improving this further can get the info for their code Differential revision: https://reviews.llvm.org/D77448
2020-06-19 04:53:50 +02:00
; LE-NEXT: xxsldwi 0, 35, 35, 3
; LE-NEXT: mtvsrd 33, 3
; LE-NEXT: mffprwz 3, 1
; LE-NEXT: mtvsrd 38, 4
; LE-NEXT: mtvsrd 35, 3
; LE-NEXT: mffprwz 3, 0
; LE-NEXT: vmrghh 2, 0, 2
; LE-NEXT: mtvsrd 32, 3
[PowerPC] Fix ICE when truncating some vectors The legalizer would hit an assertion on PowerPC platform when truncating a vector whose size is not power of 2. This patch is to add a check to prevent vectors with such odd-size elements from being custom lowered. Reviewed By: Hal Finkel Differential Revision: https://reviews.llvm.org/D65261 llvm-svn: 368654
2019-08-13 09:53:29 +02:00
; LE-NEXT: addis 3, 2, .LCPI0_1@toc@ha
[PowerPC] Canonicalize shuffles to match more single-instruction masks on LE We currently miss a number of opportunities to emit single-instruction VMRG[LH][BHW] instructions for shuffles on little endian subtargets. Although this in itself is not a huge performance opportunity since loading the permute vector for a VPERM can always be pulled out of loops, producing such merge instructions is useful to downstream optimizations. Since VPERM is essentially opaque to all subsequent optimizations, we want to avoid it as much as possible. Other permute instructions have semantics that can be reasoned about much more easily in later optimizations. This patch does the following: - Canonicalize shuffles so that the first element comes from the first vector (since that's what most of the mask matching functions want) - Switch the elements that come from splat vectors so that they match the corresponding elements from the other vector (to allow for merges) - Adds debugging messages for when a shuffle is matched to a VPERM so that anyone interested in improving this further can get the info for their code Differential revision: https://reviews.llvm.org/D77448
2020-06-19 04:53:50 +02:00
; LE-NEXT: vmrghh 4, 1, 4
[PowerPC] Fix ICE when truncating some vectors The legalizer would hit an assertion on PowerPC platform when truncating a vector whose size is not power of 2. This patch is to add a check to prevent vectors with such odd-size elements from being custom lowered. Reviewed By: Hal Finkel Differential Revision: https://reviews.llvm.org/D65261 llvm-svn: 368654
2019-08-13 09:53:29 +02:00
; LE-NEXT: addi 3, 3, .LCPI0_1@toc@l
[PowerPC] Canonicalize shuffles to match more single-instruction masks on LE We currently miss a number of opportunities to emit single-instruction VMRG[LH][BHW] instructions for shuffles on little endian subtargets. Although this in itself is not a huge performance opportunity since loading the permute vector for a VPERM can always be pulled out of loops, producing such merge instructions is useful to downstream optimizations. Since VPERM is essentially opaque to all subsequent optimizations, we want to avoid it as much as possible. Other permute instructions have semantics that can be reasoned about much more easily in later optimizations. This patch does the following: - Canonicalize shuffles so that the first element comes from the first vector (since that's what most of the mask matching functions want) - Switch the elements that come from splat vectors so that they match the corresponding elements from the other vector (to allow for merges) - Adds debugging messages for when a shuffle is matched to a VPERM so that anyone interested in improving this further can get the info for their code Differential revision: https://reviews.llvm.org/D77448
2020-06-19 04:53:50 +02:00
; LE-NEXT: vmrghh 3, 3, 6
; LE-NEXT: vmrghh 5, 0, 5
; LE-NEXT: vmrglw 2, 4, 2
[PowerPC] Fix ICE when truncating some vectors The legalizer would hit an assertion on PowerPC platform when truncating a vector whose size is not power of 2. This patch is to add a check to prevent vectors with such odd-size elements from being custom lowered. Reviewed By: Hal Finkel Differential Revision: https://reviews.llvm.org/D65261 llvm-svn: 368654
2019-08-13 09:53:29 +02:00
; LE-NEXT: vspltish 4, 15
[PowerPC] Canonicalize shuffles to match more single-instruction masks on LE We currently miss a number of opportunities to emit single-instruction VMRG[LH][BHW] instructions for shuffles on little endian subtargets. Although this in itself is not a huge performance opportunity since loading the permute vector for a VPERM can always be pulled out of loops, producing such merge instructions is useful to downstream optimizations. Since VPERM is essentially opaque to all subsequent optimizations, we want to avoid it as much as possible. Other permute instructions have semantics that can be reasoned about much more easily in later optimizations. This patch does the following: - Canonicalize shuffles so that the first element comes from the first vector (since that's what most of the mask matching functions want) - Switch the elements that come from splat vectors so that they match the corresponding elements from the other vector (to allow for merges) - Adds debugging messages for when a shuffle is matched to a VPERM so that anyone interested in improving this further can get the info for their code Differential revision: https://reviews.llvm.org/D77448
2020-06-19 04:53:50 +02:00
; LE-NEXT: vmrglw 3, 5, 3
[PowerPC] Fix ICE when truncating some vectors The legalizer would hit an assertion on PowerPC platform when truncating a vector whose size is not power of 2. This patch is to add a check to prevent vectors with such odd-size elements from being custom lowered. Reviewed By: Hal Finkel Differential Revision: https://reviews.llvm.org/D65261 llvm-svn: 368654
2019-08-13 09:53:29 +02:00
; LE-NEXT: xxmrgld 34, 35, 34
; LE-NEXT: lvx 3, 0, 3
; LE-NEXT: xxlor 34, 34, 35
; LE-NEXT: vslh 2, 2, 4
; LE-NEXT: vsrah 2, 2, 4
; LE-NEXT: blr
;
; BE-LABEL: pr25080:
; BE: # %bb.0: # %entry
; BE-NEXT: addis 3, 2, .LCPI0_0@toc@ha
; BE-NEXT: xxlxor 36, 36, 36
; BE-NEXT: addi 3, 3, .LCPI0_0@toc@l
; BE-NEXT: lxvw4x 0, 0, 3
; BE-NEXT: xxland 35, 35, 0
; BE-NEXT: xxland 34, 34, 0
; BE-NEXT: vcmpequw 3, 3, 4
; BE-NEXT: vcmpequw 2, 2, 4
; BE-NEXT: xxswapd 0, 35
; BE-NEXT: mfvsrwz 3, 35
; BE-NEXT: xxsldwi 1, 35, 35, 1
; BE-NEXT: sldi 3, 3, 48
[PowerPC] Ignore implicit register operands for MCInst Summary: When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands, it will expose more opportunity for InstiAlias. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77118
2020-04-16 18:22:43 +02:00
; BE-NEXT: mffprwz 4, 0
[PowerPC] Fix ICE when truncating some vectors The legalizer would hit an assertion on PowerPC platform when truncating a vector whose size is not power of 2. This patch is to add a check to prevent vectors with such odd-size elements from being custom lowered. Reviewed By: Hal Finkel Differential Revision: https://reviews.llvm.org/D65261 llvm-svn: 368654
2019-08-13 09:53:29 +02:00
; BE-NEXT: xxsldwi 0, 35, 35, 3
; BE-NEXT: mtvsrd 36, 3
[PowerPC] Ignore implicit register operands for MCInst Summary: When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands, it will expose more opportunity for InstiAlias. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77118
2020-04-16 18:22:43 +02:00
; BE-NEXT: mffprwz 3, 1
[PowerPC] Fix ICE when truncating some vectors The legalizer would hit an assertion on PowerPC platform when truncating a vector whose size is not power of 2. This patch is to add a check to prevent vectors with such odd-size elements from being custom lowered. Reviewed By: Hal Finkel Differential Revision: https://reviews.llvm.org/D65261 llvm-svn: 368654
2019-08-13 09:53:29 +02:00
; BE-NEXT: sldi 4, 4, 48
; BE-NEXT: xxswapd 1, 34
; BE-NEXT: mtvsrd 35, 4
; BE-NEXT: mfvsrwz 4, 34
; BE-NEXT: sldi 3, 3, 48
; BE-NEXT: mtvsrd 37, 3
[PowerPC] Ignore implicit register operands for MCInst Summary: When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands, it will expose more opportunity for InstiAlias. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77118
2020-04-16 18:22:43 +02:00
; BE-NEXT: mffprwz 3, 0
[PowerPC] Fix ICE when truncating some vectors The legalizer would hit an assertion on PowerPC platform when truncating a vector whose size is not power of 2. This patch is to add a check to prevent vectors with such odd-size elements from being custom lowered. Reviewed By: Hal Finkel Differential Revision: https://reviews.llvm.org/D65261 llvm-svn: 368654
2019-08-13 09:53:29 +02:00
; BE-NEXT: sldi 4, 4, 48
; BE-NEXT: xxsldwi 0, 34, 34, 1
; BE-NEXT: vmrghh 3, 5, 3
; BE-NEXT: mtvsrd 37, 4
; BE-NEXT: sldi 3, 3, 48
[PowerPC] Ignore implicit register operands for MCInst Summary: When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands, it will expose more opportunity for InstiAlias. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77118
2020-04-16 18:22:43 +02:00
; BE-NEXT: mffprwz 4, 1
[PowerPC] Fix ICE when truncating some vectors The legalizer would hit an assertion on PowerPC platform when truncating a vector whose size is not power of 2. This patch is to add a check to prevent vectors with such odd-size elements from being custom lowered. Reviewed By: Hal Finkel Differential Revision: https://reviews.llvm.org/D65261 llvm-svn: 368654
2019-08-13 09:53:29 +02:00
; BE-NEXT: xxsldwi 1, 34, 34, 3
; BE-NEXT: mtvsrd 34, 3
[PowerPC] Ignore implicit register operands for MCInst Summary: When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands, it will expose more opportunity for InstiAlias. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77118
2020-04-16 18:22:43 +02:00
; BE-NEXT: mffprwz 3, 0
[PowerPC] Fix ICE when truncating some vectors The legalizer would hit an assertion on PowerPC platform when truncating a vector whose size is not power of 2. This patch is to add a check to prevent vectors with such odd-size elements from being custom lowered. Reviewed By: Hal Finkel Differential Revision: https://reviews.llvm.org/D65261 llvm-svn: 368654
2019-08-13 09:53:29 +02:00
; BE-NEXT: sldi 4, 4, 48
; BE-NEXT: mtvsrd 32, 4
[PowerPC] Ignore implicit register operands for MCInst Summary: When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands, it will expose more opportunity for InstiAlias. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77118
2020-04-16 18:22:43 +02:00
; BE-NEXT: mffprwz 4, 1
[PowerPC] Fix ICE when truncating some vectors The legalizer would hit an assertion on PowerPC platform when truncating a vector whose size is not power of 2. This patch is to add a check to prevent vectors with such odd-size elements from being custom lowered. Reviewed By: Hal Finkel Differential Revision: https://reviews.llvm.org/D65261 llvm-svn: 368654
2019-08-13 09:53:29 +02:00
; BE-NEXT: sldi 3, 3, 48
; BE-NEXT: mtvsrd 33, 3
; BE-NEXT: sldi 3, 4, 48
; BE-NEXT: vmrghh 2, 2, 4
; BE-NEXT: mtvsrd 36, 3
; BE-NEXT: addis 3, 2, .LCPI0_1@toc@ha
; BE-NEXT: vmrghh 0, 1, 0
; BE-NEXT: addi 3, 3, .LCPI0_1@toc@l
; BE-NEXT: vmrghh 4, 4, 5
; BE-NEXT: lxvw4x 0, 0, 3
; BE-NEXT: vmrghw 2, 2, 3
; BE-NEXT: vmrghw 3, 4, 0
; BE-NEXT: xxmrghd 34, 35, 34
; BE-NEXT: vspltish 3, 15
; BE-NEXT: xxlor 34, 34, 0
; BE-NEXT: vslh 2, 2, 3
; BE-NEXT: vsrah 2, 2, 3
; BE-NEXT: blr
entry:
%0 = trunc <8 x i32> %a to <8 x i23>
%1 = icmp eq <8 x i23> %0, zeroinitializer
%2 = or <8 x i1> %1, <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>
%3 = sext <8 x i1> %2 to <8 x i16>
ret <8 x i16> %3
}
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