2019-07-04 03:51:47 +02:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s
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define void @f(i8*, i8*, i64*) {
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; Check we don't assert and this is not a Hardware Loop
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; CHECK-LABEL: f:
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2019-10-21 19:45:51 +02:00
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmpld 3, 4
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; CHECK-NEXT: beqlr 0
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: ld 6, 8(5)
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; CHECK-NEXT: not 3, 3
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; CHECK-NEXT: add 3, 3, 4
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; CHECK-NEXT: li 4, 0
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; CHECK-NEXT: .p2align 5
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[Power9] Add addi post-ra scheduling heuristic
The instruction addi is usually used to post increase the loop indvar, which looks like this:
label_X:
load x, base(i)
...
y = op x
...
i = addi i, 1
goto label_X
However, for PowerPC, if there are too many vsx instructions that between y = op x and i = addi i, 1,
it will use all the hw resource that block the execution of i = addi, i, 1, which result in the stall
of the load instruction in next iteration. So, a heuristic is added to move the addi as early as possible
to have the load hide the latency of vsx instructions, if other heuristic didn't apply to avoid the starve.
Reviewed By: jji
Differential Revision: https://reviews.llvm.org/D80269
2020-06-08 03:31:07 +02:00
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; CHECK-NEXT: .LBB0_2:
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; CHECK-NEXT: addi 7, 4, 1
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2019-10-21 19:45:51 +02:00
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; CHECK-NEXT: sldi 6, 6, 4
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2019-10-22 14:20:38 +02:00
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; CHECK-NEXT: cmplwi 4, 14
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; CHECK-NEXT: bc 12, 1, .LBB0_4
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[Power9] Add addi post-ra scheduling heuristic
The instruction addi is usually used to post increase the loop indvar, which looks like this:
label_X:
load x, base(i)
...
y = op x
...
i = addi i, 1
goto label_X
However, for PowerPC, if there are too many vsx instructions that between y = op x and i = addi i, 1,
it will use all the hw resource that block the execution of i = addi, i, 1, which result in the stall
of the load instruction in next iteration. So, a heuristic is added to move the addi as early as possible
to have the load hide the latency of vsx instructions, if other heuristic didn't apply to avoid the starve.
Reviewed By: jji
Differential Revision: https://reviews.llvm.org/D80269
2020-06-08 03:31:07 +02:00
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; CHECK-NEXT: # %bb.3:
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2019-10-22 14:20:38 +02:00
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; CHECK-NEXT: cmpd 3, 4
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; CHECK-NEXT: mr 4, 7
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; CHECK-NEXT: bc 4, 2, .LBB0_2
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; CHECK-NEXT: .LBB0_4:
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2019-10-21 19:45:51 +02:00
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; CHECK-NEXT: std 6, 8(5)
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; CHECK-NEXT: blr
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2019-07-04 03:51:47 +02:00
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%4 = icmp eq i8* %0, %1
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br i1 %4, label %9, label %5
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5: ; preds = %3
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%6 = getelementptr inbounds i64, i64* %2, i64 1
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%7 = load i64, i64* %6, align 8
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br label %10
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8: ; preds = %10
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store i64 %14, i64* %6, align 8
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br label %9
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9: ; preds = %8, %3
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ret void
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10: ; preds = %5, %10
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%11 = phi i64 [ %7, %5 ], [ %14, %10 ]
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%12 = phi i32 [ 0, %5 ], [ %15, %10 ]
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%13 = phi i8* [ %0, %5 ], [ %16, %10 ]
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%14 = shl nsw i64 %11, 4
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%15 = add nuw nsw i32 %12, 1
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%16 = getelementptr inbounds i8, i8* %13, i64 1
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%17 = icmp ugt i32 %12, 14
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%18 = icmp eq i8* %16, %1
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%19 = or i1 %18, %17
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br i1 %19, label %8, label %10
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}
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