2019-10-03 19:13:39 +00:00
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add_subdirectory(GlobalISel)
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2011-11-02 05:03:06 +00:00
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set(LLVM_LINK_COMPONENTS Support)
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2010-10-17 02:26:16 +00:00
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2011-10-06 01:51:51 +00:00
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add_tablegen(llvm-tblgen LLVM
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2009-07-11 21:53:14 +00:00
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AsmMatcherEmitter.cpp
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2008-09-22 01:08:49 +00:00
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AsmWriterEmitter.cpp
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2010-02-09 22:29:16 +00:00
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AsmWriterInst.cpp
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2015-11-11 20:35:42 +00:00
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Attributes.cpp
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2008-09-22 01:08:49 +00:00
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CallingConvEmitter.cpp
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CodeEmitterGen.cpp
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CodeGenDAGPatterns.cpp
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2017-09-14 16:56:21 +00:00
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CodeGenHwModes.cpp
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2008-09-22 01:08:49 +00:00
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CodeGenInstruction.cpp
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2012-10-25 15:57:56 +00:00
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CodeGenMapTable.cpp
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2011-06-09 18:42:07 +00:00
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CodeGenRegisters.cpp
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2012-07-07 04:00:00 +00:00
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CodeGenSchedule.cpp
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2008-09-22 01:08:49 +00:00
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CodeGenTarget.cpp
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DAGISelEmitter.cpp
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2010-02-15 08:04:42 +00:00
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DAGISelMatcherEmitter.cpp
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DAGISelMatcherGen.cpp
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2010-02-24 07:06:50 +00:00
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DAGISelMatcherOpt.cpp
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2010-02-15 08:04:42 +00:00
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DAGISelMatcher.cpp
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2019-10-04 09:03:36 +00:00
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DFAEmitter.cpp
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2011-12-01 21:53:39 +00:00
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DFAPacketizerEmitter.cpp
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[openmp] Base of tablegen generated OpenMP common declaration
Summary:
As discussed previously when landing patch for OpenMP in Flang, the idea is
to share common part of the OpenMP declaration between the different Frontend.
While doing this it was thought that moving to tablegen instead of Macros will also
give a cleaner and more powerful way of generating these declaration.
This first part of a future series of patches is setting up the base .td file for
DirectiveLanguage as well as the OpenMP version of it. The base file is meant to
be used by other directive language such as OpenACC.
In this first patch, the Directive and Clause enums are generated with tablegen
instead of the macros on OMPConstants.h. The next pacth will extend this
to other enum and move the Flang frontend to use it.
Reviewers: jdoerfert, DavidTruby, fghanim, ABataev, jdenny, hfinkel, jhuber6, kiranchandramohan, kiranktp
Reviewed By: jdoerfert, jdenny
Subscribers: arphaman, martong, cfe-commits, mgorny, yaxunl, hiraditya, guansong, jfb, sstefan1, aaron.ballman, llvm-commits
Tags: #llvm, #openmp, #clang
Differential Revision: https://reviews.llvm.org/D81736
2020-06-23 09:29:50 -04:00
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DirectiveEmitter.cpp
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2009-11-25 02:13:23 +00:00
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DisassemblerEmitter.cpp
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2018-10-25 07:44:01 +00:00
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ExegesisEmitter.cpp
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2009-03-16 17:04:14 +00:00
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FastISelEmitter.cpp
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2011-02-18 22:06:23 +00:00
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FixedLenDecoderEmitter.cpp
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2019-10-02 21:13:07 +00:00
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GICombinerEmitter.cpp
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2016-12-21 23:26:20 +00:00
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GlobalISelEmitter.cpp
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2017-09-14 16:56:21 +00:00
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InfoByHwMode.cpp
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2008-09-22 01:08:49 +00:00
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InstrInfoEmitter.cpp
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2017-11-14 15:35:15 +00:00
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InstrDocsEmitter.cpp
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2008-09-22 01:08:49 +00:00
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IntrinsicEmitter.cpp
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2019-11-22 14:07:21 -08:00
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OptEmitter.cpp
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2012-12-05 00:29:32 +00:00
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OptParserEmitter.cpp
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2019-11-22 14:07:21 -08:00
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OptRSTEmitter.cpp
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2018-05-25 15:55:37 +00:00
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PredicateExpander.cpp
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2011-07-08 17:36:35 +00:00
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PseudoLoweringEmitter.cpp
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[RISCV] Tablegen-driven Instruction Compression.
Summary:
This patch implements a tablegen-driven Instruction Compression
mechanism for generating RISCV compressed instructions
(C Extension) from the expanded instruction form.
This tablegen backend processes CompressPat declarations in a
td file and generates all the compile-time and runtime checks
required to validate the declarations, validate the input
operands and generate correct instructions.
The checks include validating register operands, immediate
operands, fixed register operands and fixed immediate operands.
Example:
class CompressPat<dag input, dag output> {
dag Input = input;
dag Output = output;
list<Predicate> Predicates = [];
}
let Predicates = [HasStdExtC] in {
def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2),
(C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
}
The result is an auto-generated header file
'RISCVGenCompressEmitter.inc' which exports two functions for
compressing/uncompressing MCInst instructions, plus
some helper functions:
bool compressInst(MCInst& OutInst, const MCInst &MI,
const MCSubtargetInfo &STI,
MCContext &Context);
bool uncompressInst(MCInst& OutInst, const MCInst &MI,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI);
The clients that include this auto-generated header file and
invoke these functions can compress an instruction before emitting
it, in the target-specific ASM or ELF streamer, or can uncompress
an instruction before printing it, when the expanded instruction
format aliases is favored.
The following clients were added to implement compression\uncompression
for RISCV:
1) RISCVAsmParser::MatchAndEmitInstruction:
Inserted a call to compressInst() to compresses instructions
parsed by llvm-mc coming from an ASM input.
2) RISCVAsmPrinter::EmitInstruction:
Inserted a call to compressInst() to compress instructions that
were lowered from Machine Instructions (MachineInstr).
3) RVInstPrinter::printInst:
Inserted a call to uncompressInst() to print the expanded
version of the instruction instead of the compressed one (e.g,
add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases
is not passed.
This patch squashes D45119, D42780 and D41932. It was reviewed in smaller patches by
asb, efriedma, apazos and mgrang.
Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal
Reviewed By: sabuasal
Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng
Differential Revision: https://reviews.llvm.org/D45385
llvm-svn: 329455
2018-04-06 21:07:05 +00:00
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RISCVCompressInstEmitter.cpp
|
Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Changes since first commit attempt:
* Added missing guards
* Added more missing guards
* Found and fixed a use-after-free bug involving Twine locals
Reviewers: t.p.northover, ab, rovka, qcolombet
Reviewed By: qcolombet
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27338
llvm-svn: 292478
2017-01-19 11:15:55 +00:00
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RegisterBankEmitter.cpp
|
2008-09-22 01:08:49 +00:00
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RegisterInfoEmitter.cpp
|
2017-12-20 19:36:28 +00:00
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SDNodeProperties.cpp
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2016-07-05 21:23:04 +00:00
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SearchableTableEmitter.cpp
|
2008-09-22 01:08:49 +00:00
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SubtargetEmitter.cpp
|
2016-11-15 09:51:02 +00:00
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SubtargetFeatureInfo.cpp
|
2008-09-22 01:08:49 +00:00
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TableGen.cpp
|
2016-11-19 12:21:34 +00:00
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Types.cpp
|
2009-12-19 02:59:52 +00:00
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X86DisassemblerTables.cpp
|
2017-03-07 08:11:19 +00:00
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X86EVEX2VEXTablesEmitter.cpp
|
2017-10-08 09:20:32 +00:00
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X86FoldTablesEmitter.cpp
|
2011-12-20 08:42:11 +00:00
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X86ModRMFilters.cpp
|
2009-12-19 02:59:52 +00:00
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X86RecognizableInstr.cpp
|
2018-05-10 22:16:44 +00:00
|
|
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WebAssemblyDisassemblerEmitter.cpp
|
2013-03-21 23:40:38 +00:00
|
|
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CTagsEmitter.cpp
|
2008-09-22 01:08:49 +00:00
|
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|
)
|
2019-10-03 19:13:39 +00:00
|
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target_link_libraries(llvm-tblgen PRIVATE LLVMTableGenGlobalISel)
|
2017-11-04 20:07:16 +00:00
|
|
|
set_target_properties(llvm-tblgen PROPERTIES FOLDER "Tablegenning")
|