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llvm-mirror/test/MC/X86/x86-32.s

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rip out the 'heinous' x86 MCCodeEmitter implementation. We still have the templated X86 JIT emitter, *and* the almost-copy in X86InstrInfo for getting instruction sizes. llvm-svn: 96059
2010-02-13 01:49:29 +01:00
// RUN: llvm-mc -triple i386-unknown-unknown --show-encoding %s | FileCheck %s
fix the encodings of monitor and mwait, which were completely busted in both encoders. I'm not bothering to fix it in the old one at this point. llvm-svn: 95947
2010-02-12 02:06:22 +01:00
Define the x86 pause instruction. llvm-svn: 104204
2010-05-20 03:35:50 +02:00
pause
// CHECK: pause
// CHECK: encoding: [0xf3,0x90]
Fix the sfence instruction to use MRM_F8 instead of MRM7r, since it doesn't have a register operand. Also, use I instead of PSI, for consistency with mfence and lfence. llvm-svn: 104203
2010-05-20 03:23:41 +02:00
sfence
// CHECK: sfence
// CHECK: encoding: [0x0f,0xae,0xf8]
fix the encodings of monitor and mwait, which were completely busted in both encoders. I'm not bothering to fix it in the old one at this point. llvm-svn: 95947
2010-02-12 02:06:22 +01:00
lfence
// CHECK: lfence
// CHECK: encoding: [0x0f,0xae,0xe8]
mfence
// CHECK: mfence
// CHECK: encoding: [0x0f,0xae,0xf0]
monitor
// CHECK: monitor
// CHECK: encoding: [0x0f,0x01,0xc8]
mwait
// CHECK: mwait
remove special cases for vmlaunch, vmresume, vmxoff, and swapgs fix swapgs to be spelled right. llvm-svn: 96058
2010-02-13 01:41:14 +01:00
// CHECK: encoding: [0x0f,0x01,0xc9]
vmcall
// CHECK: vmcall
// CHECK: encoding: [0x0f,0x01,0xc1]
vmlaunch
// CHECK: vmlaunch
// CHECK: encoding: [0x0f,0x01,0xc2]
vmresume
// CHECK: vmresume
// CHECK: encoding: [0x0f,0x01,0xc3]
vmxoff
// CHECK: vmxoff
// CHECK: encoding: [0x0f,0x01,0xc4]
swapgs
// CHECK: swapgs
// CHECK: encoding: [0x0f,0x01,0xf8]
MC/AsmParser: Attempt to constant fold expressions up-front. This ensures we avoid fixups for obvious cases like '-(16)'. llvm-svn: 96064
2010-02-13 02:28:07 +01:00
add encoder support and tests for rdtscp llvm-svn: 96076
2010-02-13 04:42:24 +01:00
rdtscp
// CHECK: rdtscp
// CHECK: encoding: [0x0f,0x01,0xf9]
MC/AsmParser: Attempt to constant fold expressions up-front. This ensures we avoid fixups for obvious cases like '-(16)'. llvm-svn: 96064
2010-02-13 02:28:07 +01:00
// CHECK: movl %eax, 16(%ebp) # encoding: [0x89,0x45,0x10]
movl %eax, 16(%ebp)
// CHECK: movl %eax, -16(%ebp) # encoding: [0x89,0x45,0xf0]
movl %eax, -16(%ebp)
X86: Fix encoding for TEST{8,16,32}rr. llvm-svn: 97982
2010-03-08 22:10:36 +01:00
// CHECK: testb %bl, %cl # encoding: [0x84,0xcb]
testb %bl, %cl
MC/X86: Rename alternate spellings of CMP{8,16,32} and mark as "code gen only" so they don't get selected by the asm matcher. llvm-svn: 98097
2010-03-09 23:50:40 +01:00
// CHECK: cmpl %eax, %ebx # encoding: [0x39,0xc3]
cmpl %eax, %ebx
MC/X86: Rename alternate spellings of ADD{8,16,32} and mark as "code gen only" so they don't get selected by the asm matcher. llvm-svn: 98098
2010-03-09 23:50:46 +01:00
// CHECK: addw %ax, %ax # encoding: [0x66,0x01,0xc0]
addw %ax, %ax
MC/X86: Add temporary hack to match shrl $1,%eax correctly, to support testing other functionality on 403.gcc compiled at -O0. llvm-svn: 98405
2010-03-13 01:47:29 +01:00
// CHECK: shrl %eax # encoding: [0xd1,0xe8]
shrl $1, %eax
fix the encoding of the obscure "moffset" forms of moves, i386 part first. rdar://7947184 llvm-svn: 103660
2010-05-13 00:48:24 +02:00
fix an encoding mismatch where "sal %eax, 1" was not using the short encoding for shl. Caught by inspection. llvm-svn: 117820
2010-10-30 20:13:10 +02:00
// CHECK: shll %eax # encoding: [0xd1,0xe0]
sall $1, %eax
// CHECK: shll %eax # encoding: [0xd1,0xe0]
sal $1, %eax
fix the encoding of the obscure "moffset" forms of moves, i386 part first. rdar://7947184 llvm-svn: 103660
2010-05-13 00:48:24 +02:00
// moffset forms of moves, rdar://7947184
movb 0, %al // CHECK: movb 0, %al # encoding: [0xa0,A,A,A,A]
movw 0, %ax // CHECK: movw 0, %ax # encoding: [0x66,0xa1,A,A,A,A]
movl 0, %eax // CHECK: movl 0, %eax # encoding: [0xa1,A,A,A,A]
Fix so "int3" is correctly accepted, added "into" and fixed "int" with an argument, like "int $4", to not get an Assertion error. llvm-svn: 103791
2010-05-14 21:16:02 +02:00
// rdar://7973775
into
// CHECK: into
// CHECK: encoding: [0xce]
int3
// CHECK: int3
// CHECK: encoding: [0xcc]
int $4
// CHECK: int $4
// CHECK: encoding: [0xcd,0x04]
int $255
// CHECK: int $255
// CHECK: encoding: [0xcd,0xff]
Fix assembly parsing and encoding of the pushf and popf family of instructions. llvm-svn: 104231
2010-05-20 18:16:00 +02:00
// CHECK: pushfl # encoding: [0x9c]
pushf
// CHECK: pushfl # encoding: [0x9c]
pushfl
// CHECK: popfl # encoding: [0x9d]
popf
// CHECK: popfl # encoding: [0x9d]
popfl
Added retl for 32-bit x86 and added retq for 64-bit x86. llvm-svn: 104394
2010-05-22 01:01:38 +02:00
// rdar://8014869
retl
// CHECK: ret
// CHECK: encoding: [0xc3]
MC/X86: Add aliases for CMOVcc variants. llvm-svn: 104549
2010-05-24 22:32:23 +02:00
// rdar://7973854
// CHECK: cmoval %eax, %edx
// CHECK: encoding: [0x0f,0x47,0xd0]
cmoval %eax,%edx
// CHECK: cmovael %eax, %edx
// CHECK: encoding: [0x0f,0x43,0xd0]
cmovael %eax,%edx
// CHECK: cmovbel %eax, %edx
// CHECK: encoding: [0x0f,0x46,0xd0]
cmovbel %eax,%edx
// CHECK: cmovbl %eax, %edx
// CHECK: encoding: [0x0f,0x42,0xd0]
cmovbl %eax,%edx
add a missed cmov alias, part of rdar://8416805 llvm-svn: 113693
2010-09-11 19:08:22 +02:00
// CHECK: cmovbw %bx, %bx
cmovnae %bx,%bx
MC/X86: Add aliases for CMOVcc variants. llvm-svn: 104549
2010-05-24 22:32:23 +02:00
// CHECK: cmovbel %eax, %edx
// CHECK: encoding: [0x0f,0x46,0xd0]
cmovbel %eax,%edx
// CHECK: cmovbl %eax, %edx
// CHECK: encoding: [0x0f,0x42,0xd0]
cmovcl %eax,%edx
// CHECK: cmovel %eax, %edx
// CHECK: encoding: [0x0f,0x44,0xd0]
cmovel %eax,%edx
// CHECK: cmovgl %eax, %edx
// CHECK: encoding: [0x0f,0x4f,0xd0]
cmovgl %eax,%edx
// CHECK: cmovgel %eax, %edx
// CHECK: encoding: [0x0f,0x4d,0xd0]
cmovgel %eax,%edx
// CHECK: cmovll %eax, %edx
// CHECK: encoding: [0x0f,0x4c,0xd0]
cmovll %eax,%edx
// CHECK: cmovlel %eax, %edx
// CHECK: encoding: [0x0f,0x4e,0xd0]
cmovlel %eax,%edx
// CHECK: cmovbel %eax, %edx
// CHECK: encoding: [0x0f,0x46,0xd0]
cmovnal %eax,%edx
// CHECK: cmovnel %eax, %edx
// CHECK: encoding: [0x0f,0x45,0xd0]
cmovnel %eax,%edx
// CHECK: cmovael %eax, %edx
// CHECK: encoding: [0x0f,0x43,0xd0]
cmovnbl %eax,%edx
// CHECK: cmoval %eax, %edx
// CHECK: encoding: [0x0f,0x47,0xd0]
cmovnbel %eax,%edx
// CHECK: cmovael %eax, %edx
// CHECK: encoding: [0x0f,0x43,0xd0]
cmovncl %eax,%edx
// CHECK: cmovnel %eax, %edx
// CHECK: encoding: [0x0f,0x45,0xd0]
cmovnel %eax,%edx
// CHECK: cmovlel %eax, %edx
// CHECK: encoding: [0x0f,0x4e,0xd0]
cmovngl %eax,%edx
// CHECK: cmovgel %eax, %edx
// CHECK: encoding: [0x0f,0x4d,0xd0]
cmovnl %eax,%edx
// CHECK: cmovnel %eax, %edx
// CHECK: encoding: [0x0f,0x45,0xd0]
cmovnel %eax,%edx
// CHECK: cmovlel %eax, %edx
// CHECK: encoding: [0x0f,0x4e,0xd0]
cmovngl %eax,%edx
// CHECK: cmovll %eax, %edx
// CHECK: encoding: [0x0f,0x4c,0xd0]
cmovngel %eax,%edx
// CHECK: cmovgel %eax, %edx
// CHECK: encoding: [0x0f,0x4d,0xd0]
cmovnll %eax,%edx
// CHECK: cmovgl %eax, %edx
// CHECK: encoding: [0x0f,0x4f,0xd0]
cmovnlel %eax,%edx
// CHECK: cmovnol %eax, %edx
// CHECK: encoding: [0x0f,0x41,0xd0]
cmovnol %eax,%edx
// CHECK: cmovnpl %eax, %edx
// CHECK: encoding: [0x0f,0x4b,0xd0]
cmovnpl %eax,%edx
// CHECK: cmovnsl %eax, %edx
// CHECK: encoding: [0x0f,0x49,0xd0]
cmovnsl %eax,%edx
// CHECK: cmovnel %eax, %edx
// CHECK: encoding: [0x0f,0x45,0xd0]
cmovnzl %eax,%edx
// CHECK: cmovol %eax, %edx
// CHECK: encoding: [0x0f,0x40,0xd0]
cmovol %eax,%edx
// CHECK: cmovpl %eax, %edx
// CHECK: encoding: [0x0f,0x4a,0xd0]
cmovpl %eax,%edx
// CHECK: cmovsl %eax, %edx
// CHECK: encoding: [0x0f,0x48,0xd0]
cmovsl %eax,%edx
// CHECK: cmovel %eax, %edx
// CHECK: encoding: [0x0f,0x44,0xd0]
cmovzl %eax,%edx
MC/X86: Define explicit immediate forms of cmp{ss,sd,ps,pd}. llvm-svn: 104622
2010-05-25 20:40:53 +02:00
// CHECK: cmpps $0, %xmm0, %xmm1
// CHECK: encoding: [0x0f,0xc2,0xc8,0x00]
cmpps $0, %xmm0, %xmm1
// CHECK: cmpps $0, (%eax), %xmm1
// CHECK: encoding: [0x0f,0xc2,0x08,0x00]
cmpps $0, 0(%eax), %xmm1
// CHECK: cmppd $0, %xmm0, %xmm1
// CHECK: encoding: [0x66,0x0f,0xc2,0xc8,0x00]
cmppd $0, %xmm0, %xmm1
// CHECK: cmppd $0, (%eax), %xmm1
// CHECK: encoding: [0x66,0x0f,0xc2,0x08,0x00]
cmppd $0, 0(%eax), %xmm1
// CHECK: cmpss $0, %xmm0, %xmm1
// CHECK: encoding: [0xf3,0x0f,0xc2,0xc8,0x00]
cmpss $0, %xmm0, %xmm1
// CHECK: cmpss $0, (%eax), %xmm1
// CHECK: encoding: [0xf3,0x0f,0xc2,0x08,0x00]
cmpss $0, 0(%eax), %xmm1
// CHECK: cmpsd $0, %xmm0, %xmm1
// CHECK: encoding: [0xf2,0x0f,0xc2,0xc8,0x00]
cmpsd $0, %xmm0, %xmm1
// CHECK: cmpsd $0, (%eax), %xmm1
// CHECK: encoding: [0xf2,0x0f,0xc2,0x08,0x00]
cmpsd $0, 0(%eax), %xmm1
MC/X86: Add a hack to allow recognizing 'cmpltps' and friends. llvm-svn: 104626
2010-05-25 21:49:32 +02:00
// Check matching of instructions which embed the SSE comparison code.
// CHECK: cmpps $0, %xmm0, %xmm1
// CHECK: encoding: [0x0f,0xc2,0xc8,0x00]
cmpeqps %xmm0, %xmm1
// CHECK: cmppd $1, %xmm0, %xmm1
// CHECK: encoding: [0x66,0x0f,0xc2,0xc8,0x01]
cmpltpd %xmm0, %xmm1
// CHECK: cmpss $2, %xmm0, %xmm1
// CHECK: encoding: [0xf3,0x0f,0xc2,0xc8,0x02]
cmpless %xmm0, %xmm1
// CHECK: cmppd $3, %xmm0, %xmm1
// CHECK: encoding: [0x66,0x0f,0xc2,0xc8,0x03]
cmpunordpd %xmm0, %xmm1
// CHECK: cmpps $4, %xmm0, %xmm1
// CHECK: encoding: [0x0f,0xc2,0xc8,0x04]
cmpneqps %xmm0, %xmm1
// CHECK: cmppd $5, %xmm0, %xmm1
// CHECK: encoding: [0x66,0x0f,0xc2,0xc8,0x05]
cmpnltpd %xmm0, %xmm1
// CHECK: cmpss $6, %xmm0, %xmm1
// CHECK: encoding: [0xf3,0x0f,0xc2,0xc8,0x06]
cmpnless %xmm0, %xmm1
// CHECK: cmpsd $7, %xmm0, %xmm1
// CHECK: encoding: [0xf2,0x0f,0xc2,0xc8,0x07]
cmpordsd %xmm0, %xmm1
Changed the encoding of X86 floating point stack operations where both operands are st(0). These can be encoded using an opcode for storing in st(0) or using an opcode for storing in st(i), where i can also be 0. To allow testing with the darwin assembler and get a matching binary the opcode for storing in st(0) is now used. To do this the same logical trick is use from the darwin assembler in converting things like this: fmul %st(0), %st into this: fmul %st(0) by looking for the second operand being X86::ST0 for specific floating point mnemonics then removing the second X86::ST0 operand. This also has the add benefit to allow things like: fmul %st(1), %st that llvm-mc did not assemble. llvm-svn: 104634
2010-05-25 22:52:34 +02:00
// rdar://7995856
// CHECK: fmul %st(0)
// CHECK: encoding: [0xd8,0xc8]
fmul %st(0), %st
// CHECK: fadd %st(0)
// CHECK: encoding: [0xd8,0xc0]
fadd %st(0), %st
// CHECK: fsub %st(0)
// CHECK: encoding: [0xd8,0xe0]
fsub %st(0), %st
// CHECK: fsubr %st(0)
// CHECK: encoding: [0xd8,0xe8]
fsubr %st(0), %st
// CHECK: fdivr %st(0)
// CHECK: encoding: [0xd8,0xf8]
fdivr %st(0), %st
// CHECK: fdiv %st(0)
// CHECK: encoding: [0xd8,0xf0]
fdiv %st(0), %st
Fix the x86 move to/from segment register instructions. llvm-svn: 104731
2010-05-26 22:10:45 +02:00
// radr://8017519
// CHECK: movl %cs, %eax
// CHECK: encoding: [0x8c,0xc8]
movl %cs, %eax
// CHECK: movw %cs, %ax
// CHECK: encoding: [0x66,0x8c,0xc8]
movw %cs, %ax
// CHECK: movl %cs, (%eax)
// CHECK: encoding: [0x8c,0x08]
movl %cs, (%eax)
// CHECK: movw %cs, (%eax)
// CHECK: encoding: [0x66,0x8c,0x08]
movw %cs, (%eax)
// CHECK: movl %eax, %cs
// CHECK: encoding: [0x8e,0xc8]
movl %eax, %cs
// CHECK: movl (%eax), %cs
// CHECK: encoding: [0x8e,0x08]
movl (%eax), %cs
// CHECK: movw (%eax), %cs
// CHECK: encoding: [0x66,0x8e,0x08]
movw (%eax), %cs
Fix the use of x86 control and debug registers so that the assertion failure in getX86RegNum() does not happen. Patch by Shantonu Sen! llvm-svn: 104994
2010-05-28 21:01:27 +02:00
// radr://8033374
// CHECK: movl %cr0, %eax
// CHECK: encoding: [0x0f,0x20,0xc0]
movl %cr0,%eax
// CHECK: movl %cr1, %eax
// CHECK: encoding: [0x0f,0x20,0xc8]
movl %cr1,%eax
// CHECK: movl %cr2, %eax
// CHECK: encoding: [0x0f,0x20,0xd0]
movl %cr2,%eax
// CHECK: movl %cr3, %eax
// CHECK: encoding: [0x0f,0x20,0xd8]
movl %cr3,%eax
// CHECK: movl %cr4, %eax
// CHECK: encoding: [0x0f,0x20,0xe0]
movl %cr4,%eax
// CHECK: movl %dr0, %eax
// CHECK: encoding: [0x0f,0x21,0xc0]
movl %dr0,%eax
// CHECK: movl %dr1, %eax
// CHECK: encoding: [0x0f,0x21,0xc8]
movl %dr1,%eax
// CHECK: movl %dr1, %eax
// CHECK: encoding: [0x0f,0x21,0xc8]
movl %dr1,%eax
// CHECK: movl %dr2, %eax
// CHECK: encoding: [0x0f,0x21,0xd0]
movl %dr2,%eax
// CHECK: movl %dr3, %eax
// CHECK: encoding: [0x0f,0x21,0xd8]
movl %dr3,%eax
// CHECK: movl %dr4, %eax
// CHECK: encoding: [0x0f,0x21,0xe0]
movl %dr4,%eax
// CHECK: movl %dr5, %eax
// CHECK: encoding: [0x0f,0x21,0xe8]
movl %dr5,%eax
// CHECK: movl %dr6, %eax
// CHECK: encoding: [0x0f,0x21,0xf0]
movl %dr6,%eax
// CHECK: movl %dr7, %eax
// CHECK: encoding: [0x0f,0x21,0xf8]
movl %dr7,%eax
MC/X86: Add alias for fwait. llvm-svn: 105001
2010-05-28 22:59:10 +02:00
// radr://8017522
// CHECK: wait
// CHECK: encoding: [0x9b]
fwait
fix rdar://7873482 by teaching the instruction encoder to emit segment prefixes. Daniel wrote most of this patch. llvm-svn: 106364
2010-06-19 02:34:00 +02:00
// rdar://7873482
// CHECK: [0x65,0x8b,0x05,0x7c,0x00,0x00,0x00]
// FIXME: This is a correct bug poor encoding: Use 65 a1 7c 00 00 00
movl %gs:124, %eax
Add support for the x86 instructions "pusha" and "popa". llvm-svn: 106671
2010-06-23 22:00:58 +02:00
// CHECK: pusha
// CHECK: encoding: [0x60]
pusha
// CHECK: popa
// CHECK: encoding: [0x61]
popa
// CHECK: pushal
// CHECK: encoding: [0x60]
pushal
// CHECK: popal
// CHECK: encoding: [0x61]
popal
X86: Mark JMP{32,64}[mr] as requires 32-bit/64-bit mode. They are the same instruction, we only want to allow the one for the current subtarget. - This also fixes suffix matching for jmp instructions, because it eliminates the ambiguity between 'jmpl' and 'jmpq'. llvm-svn: 108746
2010-07-19 22:44:16 +02:00
// CHECK: jmpl *8(%eax)
// CHECK: encoding: [0xff,0x60,0x08]
jmp *8(%eax)
fix PR7465, mishandling of lcall and ljmp: intersegment long call and jumps. llvm-svn: 111496
2010-08-19 03:18:43 +02:00
// PR7465
// CHECK: lcalll $2, $4660
// CHECK: encoding: [0x9a,0x34,0x12,0x00,0x00,0x02,0x00]
lcalll $0x2, $0x1234
fix the encoding of the "jump on *cx" family of instructions, rdar://8061602 llvm-svn: 113343
2010-09-08 06:30:51 +02:00
// rdar://8061602
L1:
jcxz L1
// CHECK: jcxz L1
// CHECK: encoding: [0x67,0xe3,A]
jecxz L1
// CHECK: jecxz L1
// CHECK: encoding: [0xe3,A]
implement the iret suite of instructions properly, fixing rdar://8403974 llvm-svn: 113349
2010-09-08 07:38:31 +02:00
// rdar://8403974
iret
// CHECK: iretl
// CHECK: encoding: [0xcf]
iretw
// CHECK: iretw
// CHECK: encoding: [0x66,0xcf]
iretl
// CHECK: iretl
// CHECK: encoding: [0xcf]
implement proper support for sysret{,l,q}, rdar://8403907 llvm-svn: 113350
2010-09-08 07:45:34 +02:00
// rdar://8403907
sysret
// CHECK: sysretl
// CHECK: encoding: [0x0f,0x07]
sysretl
// CHECK: sysretl
// CHECK: encoding: [0x0f,0x07]
add support for the commuted form of the test instruction, rdar://8018260. llvm-svn: 113352
2010-09-08 07:51:12 +02:00
// rdar://8018260
testl %ecx, -24(%ebp)
// CHECK: testl -24(%ebp), %ecx
testl -24(%ebp), %ecx
// CHECK: testl -24(%ebp), %ecx
fix bugs in push/pop segment support, rdar://8407242 llvm-svn: 113422
2010-09-09 00:13:08 +02:00
// rdar://8407242
push %cs
// CHECK: pushl %cs
// CHECK: encoding: [0x0e]
push %ds
// CHECK: pushl %ds
// CHECK: encoding: [0x1e]
push %ss
// CHECK: pushl %ss
// CHECK: encoding: [0x16]
push %es
// CHECK: pushl %es
// CHECK: encoding: [0x06]
push %fs
// CHECK: pushl %fs
// CHECK: encoding: [0x0f,0xa0]
push %gs
// CHECK: pushl %gs
// CHECK: encoding: [0x0f,0xa8]
pushw %cs
// CHECK: pushw %cs
// CHECK: encoding: [0x66,0x0e]
pushw %ds
// CHECK: pushw %ds
// CHECK: encoding: [0x66,0x1e]
pushw %ss
// CHECK: pushw %ss
// CHECK: encoding: [0x66,0x16]
pushw %es
// CHECK: pushw %es
// CHECK: encoding: [0x66,0x06]
pushw %fs
// CHECK: pushw %fs
// CHECK: encoding: [0x66,0x0f,0xa0]
pushw %gs
// CHECK: pushw %gs
// CHECK: encoding: [0x66,0x0f,0xa8]
pop %ss
// CHECK: popl %ss
// CHECK: encoding: [0x17]
pop %ds
// CHECK: popl %ds
// CHECK: encoding: [0x1f]
pop %es
// CHECK: popl %es
// CHECK: encoding: [0x07]
add support for pushfd/popfd which are aliases for pushfl/popfl. This fixes rdar://8408129 - pushfd and popfd get invalid instruction mnemonic errors llvm-svn: 113690
2010-09-11 18:39:16 +02:00
// rdar://8408129
pushfd
// CHECK: pushfl
popfd
// CHECK: popfl
pushfl
// CHECK: pushfl
popfl
// CHECK: popfl
add support for all the setCC aliases. Part of rdar://8416805 llvm-svn: 113692
2010-09-11 19:06:05 +02:00
// rdar://8416805
setc %bl
setnae %bl
setnb %bl
setnc %bl
setna %bl
setnbe %bl
setpe %bl
setpo %bl
setnge %bl
setnl %bl
setng %bl
setnle %bl
apparently jmpl $1,$2 is an alias for ljmpl, similiarly for call. Add this. llvm-svn: 113948
2010-09-15 07:25:21 +02:00
// CHECK: lcalll $31438, $31438
// CHECK: lcalll $31438, $31438
// CHECK: ljmpl $31438, $31438
// CHECK: ljmpl $31438, $31438
calll $0x7ace,$0x7ace
lcalll $0x7ace,$0x7ace
jmpl $0x7ace,$0x7ace
ljmpl $0x7ace,$0x7ace
lcall and ljmp always default to lcalll and ljmpl. This finally wraps up r8418316 llvm-svn: 113949
2010-09-15 07:30:20 +02:00
// CHECK: lcalll $31438, $31438
// CHECK: lcalll $31438, $31438
// CHECK: ljmpl $31438, $31438
// CHECK: ljmpl $31438, $31438
call $0x7ace,$0x7ace
lcall $0x7ace,$0x7ace
jmp $0x7ace,$0x7ace
ljmp $0x7ace,$0x7ace
Fix an inconsistency in the x86 backend that led it to reject "calll foo" on x86-32: 32-bit calls were named "call" not "calll". 64-bit calls were correctly named "callq", so this only impacted x86-32. This fixes rdar://8456370 - llvm-mc rejects 'calll' This also exposes that mingw/64 is generating a 32-bit call instead of a 64-bit call, I will file a bugzilla. llvm-svn: 114534
2010-09-22 07:49:14 +02:00
// rdar://8456370
// CHECK: calll a
calll a
merge and clean up tests. llvm-svn: 115177
2010-09-30 19:24:05 +02:00
// CHECK: incb %al # encoding: [0xfe,0xc0]
incb %al
// CHECK: incw %ax # encoding: [0x66,0x40]
incw %ax
// CHECK: incl %eax # encoding: [0x40]
incl %eax
// CHECK: decb %al # encoding: [0xfe,0xc8]
decb %al
// CHECK: decw %ax # encoding: [0x66,0x48]
decw %ax
// CHECK: decl %eax # encoding: [0x48]
decl %eax
fix a regression introduced in r115243, in which the instruction backing int_x86_ssse3_pshuf_w got removed. This caused PR8280. llvm-svn: 115422
2010-10-02 23:32:15 +02:00
// CHECK: pshufw $14, %mm4, %mm0 # encoding: [0x0f,0x70,0xc4,0x0e]
pshufw $14, %mm4, %mm0
the immediate field of pshufw is actually an 8-bit field, not a 8-bit field that is sign extended. This fixes PR8288 llvm-svn: 115473
2010-10-03 21:09:13 +02:00
// CHECK: pshufw $90, %mm4, %mm0 # encoding: [0x0f,0x70,0xc4,0x5a]
// PR8288
pshufw $90, %mm4, %mm0
Added a handful of x86-32 instructions that were missing so that llvm-mc would be more complete. These are only expected to be used by llvm-mc with assembly source so there is no pattern, [], in the .td files. Most are being added to X86InstrInfo.td as Chris suggested and only comments about register uses are added. Suggestions welcome on the .td changes as I'm not sure on every detail of the x86 records. More missing instructions will be coming. llvm-svn: 116716
2010-10-18 19:04:36 +02:00
// rdar://8416805
// CHECK: aaa
// CHECK: encoding: [0x37]
aaa
// CHECK: aad $1
// CHECK: encoding: [0xd5,0x01]
aad $1
// CHECK: aad $10
// CHECK: encoding: [0xd5,0x0a]
aad $0xA
// CHECK: aad $10
// CHECK: encoding: [0xd5,0x0a]
aad
// CHECK: aam $2
// CHECK: encoding: [0xd4,0x02]
aam $2
// CHECK: aam $10
// CHECK: encoding: [0xd4,0x0a]
aam $0xA
// CHECK: aam $10
// CHECK: encoding: [0xd4,0x0a]
aam
// CHECK: aas
// CHECK: encoding: [0x3f]
aas
// CHECK: daa
// CHECK: encoding: [0x27]
daa
// CHECK: das
// CHECK: encoding: [0x2f]
das
// CHECK: retw $31438
// CHECK: encoding: [0x66,0xc2,0xce,0x7a]
retw $0x7ace
// CHECK: lretw $31438
// CHECK: encoding: [0x66,0xca,0xce,0x7a]
lretw $0x7ace
// CHECK: bound 2(%eax), %bx
// CHECK: encoding: [0x66,0x62,0x58,0x02]
bound 2(%eax),%bx
// CHECK: bound 4(%ebx), %ecx
// CHECK: encoding: [0x62,0x4b,0x04]
bound 4(%ebx),%ecx
// CHECK: arpl %bx, %bx
// CHECK: encoding: [0x63,0xdb]
arpl %bx,%bx
// CHECK: arpl %bx, 6(%ecx)
// CHECK: encoding: [0x63,0x59,0x06]
arpl %bx,6(%ecx)
Added a few tweaks to the Intel Descriptor-table support instructions to allow word forms and suffixed versions to match the darwin assembler in 32-bit and 64-bit modes. This is again for use just with assembly source for llvm-mc . llvm-svn: 116773
2010-10-19 02:01:44 +02:00
// CHECK: lgdtw 4(%eax)
// CHECK: encoding: [0x66,0x0f,0x01,0x50,0x04]
lgdtw 4(%eax)
// CHECK: lgdt 4(%eax)
// CHECK: encoding: [0x0f,0x01,0x50,0x04]
lgdt 4(%eax)
// CHECK: lgdt 4(%eax)
// CHECK: encoding: [0x0f,0x01,0x50,0x04]
lgdtl 4(%eax)
// CHECK: lidtw 4(%eax)
// CHECK: encoding: [0x66,0x0f,0x01,0x58,0x04]
lidtw 4(%eax)
// CHECK: lidt 4(%eax)
// CHECK: encoding: [0x0f,0x01,0x58,0x04]
lidt 4(%eax)
// CHECK: lidt 4(%eax)
// CHECK: encoding: [0x0f,0x01,0x58,0x04]
lidtl 4(%eax)
// CHECK: sgdtw 4(%eax)
// CHECK: encoding: [0x66,0x0f,0x01,0x40,0x04]
sgdtw 4(%eax)
// CHECK: sgdt 4(%eax)
// CHECK: encoding: [0x0f,0x01,0x40,0x04]
sgdt 4(%eax)
// CHECK: sgdt 4(%eax)
// CHECK: encoding: [0x0f,0x01,0x40,0x04]
sgdtl 4(%eax)
// CHECK: sidtw 4(%eax)
// CHECK: encoding: [0x66,0x0f,0x01,0x48,0x04]
sidtw 4(%eax)
// CHECK: sidt 4(%eax)
// CHECK: encoding: [0x0f,0x01,0x48,0x04]
sidt 4(%eax)
// CHECK: sidt 4(%eax)
// CHECK: encoding: [0x0f,0x01,0x48,0x04]
sidtl 4(%eax)
Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc will accept versions that the darwin assembler allows. Forms ending in "pi" and forms without all the operands. llvm-svn: 117427
2010-10-27 02:59:28 +02:00
change the fp comparison instructions to not have %st0 explicitly listed in its asm string, for consistency with the other similar instructions. llvm-svn: 118354
2010-11-06 21:55:09 +01:00
// CHECK: fcomip %st(2)
Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc will accept versions that the darwin assembler allows. Forms ending in "pi" and forms without all the operands. llvm-svn: 117427
2010-10-27 02:59:28 +02:00
// CHECK: encoding: [0xdf,0xf2]
fcompi %st(2),%st
change the fp comparison instructions to not have %st0 explicitly listed in its asm string, for consistency with the other similar instructions. llvm-svn: 118354
2010-11-06 21:55:09 +01:00
// CHECK: fcomip %st(2)
Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc will accept versions that the darwin assembler allows. Forms ending in "pi" and forms without all the operands. llvm-svn: 117427
2010-10-27 02:59:28 +02:00
// CHECK: encoding: [0xdf,0xf2]
fcompi %st(2)
change the fp comparison instructions to not have %st0 explicitly listed in its asm string, for consistency with the other similar instructions. llvm-svn: 118354
2010-11-06 21:55:09 +01:00
// CHECK: fcomip %st(1)
Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc will accept versions that the darwin assembler allows. Forms ending in "pi" and forms without all the operands. llvm-svn: 117427
2010-10-27 02:59:28 +02:00
// CHECK: encoding: [0xdf,0xf1]
fcompi
change the fp comparison instructions to not have %st0 explicitly listed in its asm string, for consistency with the other similar instructions. llvm-svn: 118354
2010-11-06 21:55:09 +01:00
// CHECK: fucomip %st(2)
Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc will accept versions that the darwin assembler allows. Forms ending in "pi" and forms without all the operands. llvm-svn: 117427
2010-10-27 02:59:28 +02:00
// CHECK: encoding: [0xdf,0xea]
fucompi %st(2),%st
change the fp comparison instructions to not have %st0 explicitly listed in its asm string, for consistency with the other similar instructions. llvm-svn: 118354
2010-11-06 21:55:09 +01:00
// CHECK: fucomip %st(2)
Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc will accept versions that the darwin assembler allows. Forms ending in "pi" and forms without all the operands. llvm-svn: 117427
2010-10-27 02:59:28 +02:00
// CHECK: encoding: [0xdf,0xea]
fucompi %st(2)
change the fp comparison instructions to not have %st0 explicitly listed in its asm string, for consistency with the other similar instructions. llvm-svn: 118354
2010-11-06 21:55:09 +01:00
// CHECK: fucomip %st(1)
Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc will accept versions that the darwin assembler allows. Forms ending in "pi" and forms without all the operands. llvm-svn: 117427
2010-10-27 02:59:28 +02:00
// CHECK: encoding: [0xdf,0xe9]
fucompi
Tweaks to X86 instructions to allow the 'w' suffix in places it makes sense, when the instruction takes the 16-bit ax register or m16 memory location. These changes to llvm-mc matches what the darwin assembler allows for these instructions. Done differently than in r117031 that caused a valgrind error which was later reverted. llvm-svn: 117433
2010-10-27 04:32:19 +02:00
// CHECK: fldcw 32493
// CHECK: encoding: [0xd9,0x2d,0xed,0x7e,0x00,0x00]
fldcww 0x7eed
// CHECK: fldcw 32493
// CHECK: encoding: [0xd9,0x2d,0xed,0x7e,0x00,0x00]
fldcw 0x7eed
// CHECK: fnstcw 32493
// CHECK: encoding: [0xd9,0x3d,0xed,0x7e,0x00,0x00]
fnstcww 0x7eed
// CHECK: fnstcw 32493
// CHECK: encoding: [0xd9,0x3d,0xed,0x7e,0x00,0x00]
fnstcw 0x7eed
// CHECK: wait
// CHECK: encoding: [0x9b]
fstcww 0x7eed
// CHECK: wait
// CHECK: encoding: [0x9b]
fstcw 0x7eed
// CHECK: fnstsw 32493
// CHECK: encoding: [0xdd,0x3d,0xed,0x7e,0x00,0x00]
fnstsww 0x7eed
// CHECK: fnstsw 32493
// CHECK: encoding: [0xdd,0x3d,0xed,0x7e,0x00,0x00]
fnstsw 0x7eed
// CHECK: wait
// CHECK: encoding: [0x9b]
fstsww 0x7eed
// CHECK: wait
// CHECK: encoding: [0x9b]
fstsw 0x7eed
// CHECK: verr 32493
// CHECK: encoding: [0x0f,0x00,0x25,0xed,0x7e,0x00,0x00]
verrw 0x7eed
// CHECK: verr 32493
// CHECK: encoding: [0x0f,0x00,0x25,0xed,0x7e,0x00,0x00]
verr 0x7eed
Another tweak to X86 instructions to add the missing flex instruction (without the wait prefix). llvm-svn: 117434
2010-10-27 04:53:04 +02:00
// CHECK: wait
// CHECK: encoding: [0x9b]
fclex
// CHECK: fnclex
// CHECK: encoding: [0xdb,0xe2]
fnclex
Yet another tweak to X86 instructions to add ud2a as an alias to ud2 (still to add ud2b). llvm-svn: 117435
2010-10-27 05:01:02 +02:00
add a test for the ud2a alias. llvm-svn: 117803
2010-10-30 19:01:25 +02:00
// CHECK: ud2
// CHECK: encoding: [0x0f,0x0b]
ud2
Yet another tweak to X86 instructions to add ud2a as an alias to ud2 (still to add ud2b). llvm-svn: 117435
2010-10-27 05:01:02 +02:00
// CHECK: ud2
// CHECK: encoding: [0x0f,0x0b]
ud2a
Added the x86 instruction ud2b (2nd official undefined instruction). llvm-svn: 117485
2010-10-27 22:46:49 +02:00
// CHECK: ud2b
// CHECK: encoding: [0x0f,0xb9]
ud2b
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