2017-07-26 01:51:02 +02:00
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//===- AArch64TargetTransformInfo.h - AArch64 specific TTI ------*- C++ -*-===//
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2015-01-31 12:17:59 +01:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file a TargetTransformInfo::Concept conforming object specific to the
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/// AArch64 target machine. It uses the target's detailed information to
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/// provide more precise answers to certain TTI queries, while letting the
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/// target independent and default TTI implementations handle the rest.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
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#define LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
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#include "AArch64.h"
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2017-07-26 01:51:02 +02:00
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#include "AArch64Subtarget.h"
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2015-01-31 12:17:59 +01:00
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#include "AArch64TargetMachine.h"
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2017-07-26 01:51:02 +02:00
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#include "llvm/ADT/ArrayRef.h"
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2015-01-31 12:17:59 +01:00
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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2017-07-26 01:51:02 +02:00
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Intrinsics.h"
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#include <cstdint>
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2015-01-31 12:17:59 +01:00
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namespace llvm {
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2017-07-26 01:51:02 +02:00
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class APInt;
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class Instruction;
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class IntrinsicInst;
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class Loop;
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class SCEV;
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class ScalarEvolution;
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class Type;
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class Value;
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class VectorType;
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2015-01-31 12:17:59 +01:00
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class AArch64TTIImpl : public BasicTTIImplBase<AArch64TTIImpl> {
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using BaseT = BasicTTIImplBase<AArch64TTIImpl>;
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using TTI = TargetTransformInfo;
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2015-02-01 15:01:15 +01:00
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friend BaseT;
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2015-01-31 12:17:59 +01:00
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const AArch64Subtarget *ST;
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const AArch64TargetLowering *TLI;
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2015-02-01 15:22:17 +01:00
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const AArch64Subtarget *getST() const { return ST; }
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2015-02-01 15:01:15 +01:00
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const AArch64TargetLowering *getTLI() const { return TLI; }
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2015-01-31 12:17:59 +01:00
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enum MemIntrinsicType {
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VECTOR_LDST_TWO_ELEMENTS,
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VECTOR_LDST_THREE_ELEMENTS,
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VECTOR_LDST_FOUR_ELEMENTS
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};
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2017-05-09 22:18:12 +02:00
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bool isWideningInstruction(Type *Ty, unsigned Opcode,
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ArrayRef<const Value *> Args);
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2015-01-31 12:17:59 +01:00
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public:
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2015-09-17 01:38:13 +02:00
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explicit AArch64TTIImpl(const AArch64TargetMachine *TM, const Function &F)
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2015-07-09 04:08:42 +02:00
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: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
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TLI(ST->getTargetLowering()) {}
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2015-01-31 12:17:59 +01:00
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2017-06-28 00:27:32 +02:00
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bool areInlineCompatible(const Function *Caller,
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const Function *Callee) const;
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2015-01-31 12:17:59 +01:00
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/// \name Scalar TTI Implementations
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/// @{
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using BaseT::getIntImmCost;
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2015-08-05 20:08:10 +02:00
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int getIntImmCost(int64_t Val);
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int getIntImmCost(const APInt &Imm, Type *Ty);
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int getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty);
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int getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
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Type *Ty);
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2015-01-31 12:17:59 +01:00
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TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
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/// @}
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/// \name Vector TTI Implementations
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/// @{
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2015-09-01 13:26:46 +02:00
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bool enableInterleavedAccessVectorization() { return true; }
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2015-01-31 12:17:59 +01:00
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unsigned getNumberOfRegisters(bool Vector) {
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if (Vector) {
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if (ST->hasNEON())
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return 32;
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return 0;
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}
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return 31;
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}
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Const correctness for TTI::getRegisterBitWidth
Summary: The method TargetTransformInfo::getRegisterBitWidth() is declared const, but the type erasing implementation classes (TargetTransformInfo::Concept & TargetTransformInfo::Model) that were introduced by Chandler in https://reviews.llvm.org/D7293 do not have the method declared const. This is an NFC to tidy up the const consistency between TTI and its implementation.
Reviewers: chandlerc, rnk, reames
Reviewed By: reames
Subscribers: reames, jfb, arsenm, dschuff, nemanjai, nhaehnle, javed.absar, sbc100, jgravelle-google, llvm-commits
Differential Revision: https://reviews.llvm.org/D33903
llvm-svn: 305189
2017-06-12 16:22:21 +02:00
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unsigned getRegisterBitWidth(bool Vector) const {
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2015-01-31 12:17:59 +01:00
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if (Vector) {
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if (ST->hasNEON())
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return 128;
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return 0;
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}
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return 64;
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}
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2017-05-15 23:15:01 +02:00
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unsigned getMinVectorRegisterBitWidth() {
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return ST->getMinVectorRegisterBitWidth();
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}
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2015-05-06 19:12:25 +02:00
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unsigned getMaxInterleaveFactor(unsigned VF);
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2015-01-31 12:17:59 +01:00
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2017-04-12 13:49:08 +02:00
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int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
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const Instruction *I = nullptr);
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2015-01-31 12:17:59 +01:00
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2016-04-27 17:20:21 +02:00
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int getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy,
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unsigned Index);
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2015-08-05 20:08:10 +02:00
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int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
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2015-01-31 12:17:59 +01:00
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2015-08-05 20:08:10 +02:00
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int getArithmeticInstrCost(
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2015-01-31 12:17:59 +01:00
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unsigned Opcode, Type *Ty,
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TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
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TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
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TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
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[X86] updating TTI costs for arithmetic instructions on X86\SLM arch.
updated instructions:
pmulld, pmullw, pmulhw, mulsd, mulps, mulpd, divss, divps, divsd, divpd, addpd and subpd.
special optimization case which replaces pmulld with pmullw\pmulhw\pshuf seq.
In case if the real operands bitwidth <= 16.
Differential Revision: https://reviews.llvm.org/D28104
llvm-svn: 291657
2017-01-11 09:23:37 +01:00
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TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,
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ArrayRef<const Value *> Args = ArrayRef<const Value *>());
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2015-01-31 12:17:59 +01:00
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2017-01-05 15:03:41 +01:00
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int getAddressComputationCost(Type *Ty, ScalarEvolution *SE, const SCEV *Ptr);
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2015-01-31 12:17:59 +01:00
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2017-04-12 13:49:08 +02:00
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int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
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const Instruction *I = nullptr);
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2015-01-31 12:17:59 +01:00
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2015-08-05 20:08:10 +02:00
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int getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
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2017-04-12 13:49:08 +02:00
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unsigned AddressSpace, const Instruction *I = nullptr);
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2015-01-31 12:17:59 +01:00
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2015-08-05 20:08:10 +02:00
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int getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys);
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2015-01-31 12:17:59 +01:00
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[LoopUnroll] Pass SCEV to getUnrollingPreferences hook. NFCI.
Reviewers: sanjoy, anna, reames, apilipenko, igor-laevsky, mkuper
Subscribers: jholewinski, arsenm, mzolotukhin, nemanjai, nhaehnle, javed.absar, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D34531
llvm-svn: 306554
2017-06-28 17:53:17 +02:00
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void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::UnrollingPreferences &UP);
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2015-01-31 12:17:59 +01:00
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Value *getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst,
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Type *ExpectedType);
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bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info);
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2015-08-05 20:08:10 +02:00
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int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor,
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ArrayRef<unsigned> Indices, unsigned Alignment,
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2018-10-31 10:57:56 +01:00
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unsigned AddressSpace,
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bool UseMaskForCond = false,
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bool UseMaskForGaps = false);
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2016-03-18 01:27:29 +01:00
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2017-04-03 21:20:07 +02:00
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bool
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shouldConsiderAddressTypePromotion(const Instruction &I,
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bool &AllowPromotionWithoutCommonHeader);
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2016-03-18 01:27:29 +01:00
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unsigned getCacheLineSize();
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unsigned getPrefetchDistance();
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2016-03-18 01:27:38 +01:00
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unsigned getMinPrefetchStride();
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2016-03-18 01:27:43 +01:00
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unsigned getMaxPrefetchIterationsAhead();
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2017-05-10 11:42:49 +02:00
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bool shouldExpandReduction(const IntrinsicInst *II) const {
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return false;
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}
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2017-05-16 23:29:22 +02:00
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bool useReductionIntrinsic(unsigned Opcode, Type *Ty,
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TTI::ReductionFlags Flags) const;
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2018-03-16 12:34:15 +01:00
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int getArithmeticReductionCost(unsigned Opcode, Type *Ty,
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bool IsPairwiseForm);
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2018-04-26 15:48:33 +02:00
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int getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp);
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2015-01-31 12:17:59 +01:00
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/// @}
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};
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} // end namespace llvm
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2017-07-26 01:51:02 +02:00
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#endif // LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
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