llvm-mirror/test/CodeGen/R600/fconst64.ll

; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s

; CHECK: @fconst_f64
; CHECK-DAG: S_MOV_B32 {{s[0-9]+}}, 0x40140000
; CHECK-DAG: S_MOV_B32 {{s[0-9]+}}, 0

define void @fconst_f64(double addrspace(1)* %out, double addrspace(1)* %in) {
   %r1 = load double addrspace(1)* %in
   %r2 = fadd double %r1, 5.000000e+00
   store double %r2, double addrspace(1)* %out
   ret void
}
R600/SI: Use -verify-machineinstrs for most tests We can't enable the verifier for tests with SI_IF and SI_ELSE, because these instructions are always followed by a COPY which copies their result to the next basic block. This violates the machine verifier's rule that non-terminators can not folow terminators. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 192366 2013-10-10 19:11:46 +02:00			`; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs \| FileCheck %s`
R600: Reapply testcase from r186178, the big endian issue should be fixed by r186196. llvm-svn: 186209 2013-07-12 23:54:43 +02:00
			`; CHECK: @fconst_f64`
R600/SI: Print more immediates in hex format Print in decimal for inline immediates, and hex otherwise. Use hex always for offsets in addressing offsets. This approximately matches what the shader compiler does. llvm-svn: 206335 2014-04-16 00:32:49 +02:00			`; CHECK-DAG: S_MOV_B32 {{s[0-9]+}}, 0x40140000`
R600/SI: Lower 64-bit immediates using REG_SEQUENCE llvm-svn: 205561 2014-04-03 22:19:27 +02:00			`; CHECK-DAG: S_MOV_B32 {{s[0-9]+}}, 0`
R600: Reapply testcase from r186178, the big endian issue should be fixed by r186196. llvm-svn: 186209 2013-07-12 23:54:43 +02:00
			`define void @fconst_f64(double addrspace(1)* %out, double addrspace(1)* %in) {`
			`%r1 = load double addrspace(1)* %in`
			`%r2 = fadd double %r1, 5.000000e+00`
			`store double %r2, double addrspace(1)* %out`
			`ret void`
			`}`