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llvm-mirror/test/CodeGen/ARM/fast-isel-static.ll

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Fix FileCheck --check-prefix lines. Various tests had sprung up over the years which had --check-prefix=ABC on the RUN line, but "CHECK-ABC:" later on. This happened to work before, but was strictly incorrect. FileCheck is getting stricter soon though. Patch by Ron Ofir. llvm-svn: 188173
2013-08-12 14:43:26 +02:00
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static -arm-long-calls | FileCheck -check-prefix=CHECK-LONG %s
; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static -arm-long-calls | FileCheck -check-prefix=CHECK-LONG %s
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static | FileCheck -check-prefix=CHECK-NORM %s
; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static | FileCheck -check-prefix=CHECK-NORM %s
Don't handle -arm-long-calls in fast isel for now. llvm-svn: 121919
2010-12-16 00:47:29 +01:00
define void @myadd(float* %sum, float* %addend) nounwind {
entry:
%sum.addr = alloca float*, align 4
%addend.addr = alloca float*, align 4
store float* %sum, float** %sum.addr, align 4
store float* %addend, float** %addend.addr, align 4
%tmp = load float** %sum.addr, align 4
%tmp1 = load float* %tmp
%tmp2 = load float** %addend.addr, align 4
%tmp3 = load float* %tmp2
%add = fadd float %tmp1, %tmp3
%tmp4 = load float** %sum.addr, align 4
store float %add, float* %tmp4
ret void
}
define i32 @main(i32 %argc, i8** %argv) nounwind {
entry:
%ztot = alloca float, align 4
%z = alloca float, align 4
store float 0.000000e+00, float* %ztot, align 4
store float 1.000000e+00, float* %z, align 4
Be less aggressive about hinting in RAFast. In particular, don't spill dirty registers only to satisfy a hint. It is not worth it. The attached test case provides an example where the fast allocator would spill a register when other registers are available. llvm-svn: 132900
2011-06-13 05:26:46 +02:00
; CHECK-LONG: blx r
Fix ARM FastISel tests, as a first step to enabling ARM FastISel ARM FastISel is currently only enabled for iOS non-Thumb1, and I'm working on enabling it for other targets. As a first step I've fixed some of the tests. Changes to ARM FastISel tests: - Different triples don't generate the same relocations (especially movw/movt versus constant pool loads). Use a regex to allow either. - Mangling is different. Use a regex to allow either. - The reserved registers are sometimes different, so registers get allocated in a different order. Capture the names only where this occurs. - Add -verify-machineinstrs to some tests where it works. It doesn't work everywhere it should yet. - Add -fast-isel-abort to many tests that didn't have it before. - Split out the VarArg test from fast-isel-call.ll into its own test. This simplifies test setup because of --check-prefix. Patch by JF Bastien llvm-svn: 181801
2013-05-14 18:26:38 +02:00
; CHECK-NORM: bl {{_?}}myadd
Don't handle -arm-long-calls in fast isel for now. llvm-svn: 121919
2010-12-16 00:47:29 +01:00
call void @myadd(float* %ztot, float* %z)
ret i32 0
}
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