llvm-mirror/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll

; RUN: llc -mcpu=generic -mtriple=x86_64-mingw32 < %s | FileCheck %s
; CHECK: subq    $40, %rsp
; CHECK: movaps  %xmm8, (%rsp)
; CHECK: movaps  %xmm7, 16(%rsp)

define i32 @a() nounwind {
entry:
        tail call void asm sideeffect "", "~{xmm7},~{xmm8},~{dirflag},~{fpsr},~{flags}"() nounwind
        ret i32 undef
}
Instruction scheduling itinerary for Intel Atom. Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! llvm-svn: 149558 2012-02-02 00:20:51 +01:00			`; RUN: llc -mcpu=generic -mtriple=x86_64-mingw32 < %s \| FileCheck %s`
Target/X86: Tweak allocating shadow area (aka home) on Win64. It must be enough for caller to allocate one. llvm-svn: 124949 2011-02-05 16:11:32 +01:00			`; CHECK: subq $40, %rsp`
			`; CHECK: movaps %xmm8, (%rsp)`
			`; CHECK: movaps %xmm7, 16(%rsp)`
PR3739, part 2: Use an explicit store to spill XMM registers. (Previously, the code tried to use "push", which doesn't exist for XMM registers.) llvm-svn: 72836 2009-06-04 04:32:04 +02:00
			`define i32 @a() nounwind {`
			`entry:`
Target/X86: Tweak allocating shadow area (aka home) on Win64. It must be enough for caller to allocate one. llvm-svn: 124949 2011-02-05 16:11:32 +01:00			`tail call void asm sideeffect "", "~{xmm7},~{xmm8},~{dirflag},~{fpsr},~{flags}"() nounwind`
			`ret i32 undef`
PR3739, part 2: Use an explicit store to spill XMM registers. (Previously, the code tried to use "push", which doesn't exist for XMM registers.) llvm-svn: 72836 2009-06-04 04:32:04 +02:00			`}`