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llvm-mirror/test/CodeGen/ARM/atomic-64bit.ll

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Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next. llvm-svn: 138845
2011-08-31 02:31:29 +02:00
; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s
define i64 @test1(i64* %ptr, i64 %val) {
Remove hard coded registers in ARM ldrexd and strexd instructions This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. llvm-svn: 168207
2012-11-16 22:55:34 +01:00
; CHECK: test1:
Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next. llvm-svn: 138845
2011-08-31 02:31:29 +02:00
; CHECK: dmb ish
Remove hard coded registers in ARM ldrexd and strexd instructions This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. llvm-svn: 168207
2012-11-16 22:55:34 +01:00
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
; CHECK: adds [[REG3:(r[0-9]?[02468])]], [[REG1]]
; CHECK: adc [[REG4:(r[0-9]?[13579])]], [[REG2]]
; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next. llvm-svn: 138845
2011-08-31 02:31:29 +02:00
; CHECK: cmp
; CHECK: bne
; CHECK: dmb ish
%r = atomicrmw add i64* %ptr, i64 %val seq_cst
ret i64 %r
}
define i64 @test2(i64* %ptr, i64 %val) {
Remove hard coded registers in ARM ldrexd and strexd instructions This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. llvm-svn: 168207
2012-11-16 22:55:34 +01:00
; CHECK: test2:
Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next. llvm-svn: 138845
2011-08-31 02:31:29 +02:00
; CHECK: dmb ish
Remove hard coded registers in ARM ldrexd and strexd instructions This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. llvm-svn: 168207
2012-11-16 22:55:34 +01:00
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
; CHECK: subs [[REG3:(r[0-9]?[02468])]], [[REG1]]
; CHECK: sbc [[REG4:(r[0-9]?[13579])]], [[REG2]]
; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next. llvm-svn: 138845
2011-08-31 02:31:29 +02:00
; CHECK: cmp
; CHECK: bne
; CHECK: dmb ish
%r = atomicrmw sub i64* %ptr, i64 %val seq_cst
ret i64 %r
}
define i64 @test3(i64* %ptr, i64 %val) {
Remove hard coded registers in ARM ldrexd and strexd instructions This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. llvm-svn: 168207
2012-11-16 22:55:34 +01:00
; CHECK: test3:
Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next. llvm-svn: 138845
2011-08-31 02:31:29 +02:00
; CHECK: dmb ish
Remove hard coded registers in ARM ldrexd and strexd instructions This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. llvm-svn: 168207
2012-11-16 22:55:34 +01:00
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
; CHECK: and [[REG3:(r[0-9]?[02468])]], [[REG1]]
; CHECK: and [[REG4:(r[0-9]?[13579])]], [[REG2]]
; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next. llvm-svn: 138845
2011-08-31 02:31:29 +02:00
; CHECK: cmp
; CHECK: bne
; CHECK: dmb ish
%r = atomicrmw and i64* %ptr, i64 %val seq_cst
ret i64 %r
}
define i64 @test4(i64* %ptr, i64 %val) {
Remove hard coded registers in ARM ldrexd and strexd instructions This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. llvm-svn: 168207
2012-11-16 22:55:34 +01:00
; CHECK: test4:
Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next. llvm-svn: 138845
2011-08-31 02:31:29 +02:00
; CHECK: dmb ish
Remove hard coded registers in ARM ldrexd and strexd instructions This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. llvm-svn: 168207
2012-11-16 22:55:34 +01:00
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
; CHECK: orr [[REG3:(r[0-9]?[02468])]], [[REG1]]
; CHECK: orr [[REG4:(r[0-9]?[13579])]], [[REG2]]
; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next. llvm-svn: 138845
2011-08-31 02:31:29 +02:00
; CHECK: cmp
; CHECK: bne
; CHECK: dmb ish
%r = atomicrmw or i64* %ptr, i64 %val seq_cst
ret i64 %r
}
define i64 @test5(i64* %ptr, i64 %val) {
Remove hard coded registers in ARM ldrexd and strexd instructions This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. llvm-svn: 168207
2012-11-16 22:55:34 +01:00
; CHECK: test5:
Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next. llvm-svn: 138845
2011-08-31 02:31:29 +02:00
; CHECK: dmb ish
Remove hard coded registers in ARM ldrexd and strexd instructions This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. llvm-svn: 168207
2012-11-16 22:55:34 +01:00
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
; CHECK: eor [[REG3:(r[0-9]?[02468])]], [[REG1]]
; CHECK: eor [[REG4:(r[0-9]?[13579])]], [[REG2]]
; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next. llvm-svn: 138845
2011-08-31 02:31:29 +02:00
; CHECK: cmp
; CHECK: bne
; CHECK: dmb ish
%r = atomicrmw xor i64* %ptr, i64 %val seq_cst
ret i64 %r
}
define i64 @test6(i64* %ptr, i64 %val) {
Remove hard coded registers in ARM ldrexd and strexd instructions This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. llvm-svn: 168207
2012-11-16 22:55:34 +01:00
; CHECK: test6:
Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next. llvm-svn: 138845
2011-08-31 02:31:29 +02:00
; CHECK: dmb ish
Remove hard coded registers in ARM ldrexd and strexd instructions This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. llvm-svn: 168207
2012-11-16 22:55:34 +01:00
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next. llvm-svn: 138845
2011-08-31 02:31:29 +02:00
; CHECK: cmp
; CHECK: bne
; CHECK: dmb ish
%r = atomicrmw xchg i64* %ptr, i64 %val seq_cst
ret i64 %r
Some minor cleanups for r138845. llvm-svn: 138846
2011-08-31 02:41:05 +02:00
}
64-bit atomic cmpxchg for ARM. llvm-svn: 138868
2011-08-31 19:52:22 +02:00
define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) {
Remove hard coded registers in ARM ldrexd and strexd instructions This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. llvm-svn: 168207
2012-11-16 22:55:34 +01:00
; CHECK: test7:
64-bit atomic cmpxchg for ARM. llvm-svn: 138868
2011-08-31 19:52:22 +02:00
; CHECK: dmb ish
Remove hard coded registers in ARM ldrexd and strexd instructions This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. llvm-svn: 168207
2012-11-16 22:55:34 +01:00
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
; CHECK: cmp [[REG1]]
; CHECK: cmpeq [[REG2]]
64-bit atomic cmpxchg for ARM. llvm-svn: 138868
2011-08-31 19:52:22 +02:00
; CHECK: bne
Remove hard coded registers in ARM ldrexd and strexd instructions This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. llvm-svn: 168207
2012-11-16 22:55:34 +01:00
; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
64-bit atomic cmpxchg for ARM. llvm-svn: 138868
2011-08-31 19:52:22 +02:00
; CHECK: cmp
; CHECK: bne
; CHECK: dmb ish
%r = cmpxchg i64* %ptr, i64 %val1, i64 %val2 seq_cst
ret i64 %r
}
Generic expansion for atomic load/store into cmpxchg/atomicrmw xchg; implements 64-bit atomic load/store for ARM. llvm-svn: 138872
2011-08-31 20:26:09 +02:00
; Compiles down to cmpxchg
; FIXME: Should compile to a single ldrexd
define i64 @test8(i64* %ptr) {
Remove hard coded registers in ARM ldrexd and strexd instructions This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. llvm-svn: 168207
2012-11-16 22:55:34 +01:00
; CHECK: test8:
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
; CHECK: cmp [[REG1]]
; CHECK: cmpeq [[REG2]]
Generic expansion for atomic load/store into cmpxchg/atomicrmw xchg; implements 64-bit atomic load/store for ARM. llvm-svn: 138872
2011-08-31 20:26:09 +02:00
; CHECK: bne
Remove hard coded registers in ARM ldrexd and strexd instructions This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. llvm-svn: 168207
2012-11-16 22:55:34 +01:00
; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
Generic expansion for atomic load/store into cmpxchg/atomicrmw xchg; implements 64-bit atomic load/store for ARM. llvm-svn: 138872
2011-08-31 20:26:09 +02:00
; CHECK: cmp
; CHECK: bne
; CHECK: dmb ish
%r = load atomic i64* %ptr seq_cst, align 8
ret i64 %r
}
; Compiles down to atomicrmw xchg; there really isn't any more efficient
; way to write it.
define void @test9(i64* %ptr, i64 %val) {
Remove hard coded registers in ARM ldrexd and strexd instructions This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. llvm-svn: 168207
2012-11-16 22:55:34 +01:00
; CHECK: test9:
Generic expansion for atomic load/store into cmpxchg/atomicrmw xchg; implements 64-bit atomic load/store for ARM. llvm-svn: 138872
2011-08-31 20:26:09 +02:00
; CHECK: dmb ish
Remove hard coded registers in ARM ldrexd and strexd instructions This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. llvm-svn: 168207
2012-11-16 22:55:34 +01:00
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
Generic expansion for atomic load/store into cmpxchg/atomicrmw xchg; implements 64-bit atomic load/store for ARM. llvm-svn: 138872
2011-08-31 20:26:09 +02:00
; CHECK: cmp
; CHECK: bne
; CHECK: dmb ish
store atomic i64 %val, i64* %ptr seq_cst, align 8
ret void
}
Added atomic 64 min/max/umin/umax instrinsics support in the ARM backend. llvm-svn: 168886
2012-11-29 15:41:25 +01:00
define i64 @test10(i64* %ptr, i64 %val) {
; CHECK: test10:
; CHECK: dmb ish
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
; CHECK: ble
; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
; CHECK: cmp
; CHECK: bne
; CHECK: dmb ish
%r = atomicrmw min i64* %ptr, i64 %val seq_cst
ret i64 %r
}
define i64 @test11(i64* %ptr, i64 %val) {
; CHECK: test11:
; CHECK: dmb ish
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
; CHECK: bls
; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
; CHECK: cmp
; CHECK: bne
; CHECK: dmb ish
%r = atomicrmw umin i64* %ptr, i64 %val seq_cst
ret i64 %r
}
define i64 @test12(i64* %ptr, i64 %val) {
; CHECK: test12:
; CHECK: dmb ish
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
; CHECK: bge
; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
; CHECK: cmp
; CHECK: bne
; CHECK: dmb ish
%r = atomicrmw max i64* %ptr, i64 %val seq_cst
ret i64 %r
}
define i64 @test13(i64* %ptr, i64 %val) {
; CHECK: test13:
; CHECK: dmb ish
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
; CHECK: bhs
; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
; CHECK: cmp
; CHECK: bne
; CHECK: dmb ish
%r = atomicrmw umax i64* %ptr, i64 %val seq_cst
ret i64 %r
}
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