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llvm-mirror/test/CodeGen/ARM/fnegs.ll

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Convert ARM tests to FileCheck for PR5307. llvm-svn: 89593
2009-11-22 15:23:33 +01:00
; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
switch the flag for using NEON for SP floating point to a subtarget 'feature'. Re-commit. This time complete with testsuite updates. llvm-svn: 99570
2010-03-26 00:47:34 +01:00
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0
Fix Darwin NEON FP and increase coverage llvm-svn: 177664
2013-03-21 22:30:49 +01:00
; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8
; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math | FileCheck %s -check-prefix=CORTEXA8U
; RUN: llc < %s -mtriple=arm-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8U
Convert ARM tests to FileCheck for PR5307. llvm-svn: 89593
2009-11-22 15:23:33 +01:00
; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
Add NEON single-precision FP support for fabs and fneg. llvm-svn: 78101
2009-08-04 22:39:05 +02:00
define float @test1(float* %a) {
entry:
%0 = load float* %a, align 4 ; <float> [#uses=2]
%1 = fsub float -0.000000e+00, %0 ; <float> [#uses=2]
%2 = fpext float %1 to double ; <double> [#uses=1]
%3 = fcmp olt double %2, 1.234000e+00 ; <i1> [#uses=1]
%retval = select i1 %3, float %1, float %0 ; <float> [#uses=1]
ret float %retval
}
Convert ARM tests to FileCheck for PR5307. llvm-svn: 89593
2009-11-22 15:23:33 +01:00
; VFP2: test1:
Convert -enable-sched-cycles and -enable-sched-hazard to -disable flags. They are still not enable in this revision. Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with the scheduler's model of operand latency in the selection DAG. Generalized unit tests to work with sched-cycles. llvm-svn: 123969
2011-01-21 06:51:33 +01:00
; VFP2: vneg.f32 s{{.*}}, s{{.*}}
Convert ARM tests to FileCheck for PR5307. llvm-svn: 89593
2009-11-22 15:23:33 +01:00
; NFP1: test1:
Convert -enable-sched-cycles and -enable-sched-hazard to -disable flags. They are still not enable in this revision. Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with the scheduler's model of operand latency in the selection DAG. Generalized unit tests to work with sched-cycles. llvm-svn: 123969
2011-01-21 06:51:33 +01:00
; NFP1: vneg.f32 d{{.*}}, d{{.*}}
Convert ARM tests to FileCheck for PR5307. llvm-svn: 89593
2009-11-22 15:23:33 +01:00
; NFP0: test1:
Convert -enable-sched-cycles and -enable-sched-hazard to -disable flags. They are still not enable in this revision. Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with the scheduler's model of operand latency in the selection DAG. Generalized unit tests to work with sched-cycles. llvm-svn: 123969
2011-01-21 06:51:33 +01:00
; NFP0: vneg.f32 s{{.*}}, s{{.*}}
Convert ARM tests to FileCheck for PR5307. llvm-svn: 89593
2009-11-22 15:23:33 +01:00
; CORTEXA8: test1:
Avoid NEON SP-FP unless unsafe-math or Darwin NEON is not IEEE 754 compliant, so we should avoid lowering single-precision floating point operations with NEON unless unsafe-math is turned on. The equivalent VFP instructions are IEEE 754 compliant, but in some cores they're much slower, so some archs/OSs might still request it to be on by default, such as Swift and Darwin. llvm-svn: 177651
2013-03-21 19:47:47 +01:00
; CORTEXA8: vneg.f32 s{{.*}}, s{{.*}}
; CORTEXA8U: test1:
; CORTEXA8U: vneg.f32 d{{.*}}, d{{.*}}
Convert ARM tests to FileCheck for PR5307. llvm-svn: 89593
2009-11-22 15:23:33 +01:00
; CORTEXA9: test1:
Convert -enable-sched-cycles and -enable-sched-hazard to -disable flags. They are still not enable in this revision. Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with the scheduler's model of operand latency in the selection DAG. Generalized unit tests to work with sched-cycles. llvm-svn: 123969
2011-01-21 06:51:33 +01:00
; CORTEXA9: vneg.f32 s{{.*}}, s{{.*}}
Add NEON single-precision FP support for fabs and fneg. llvm-svn: 78101
2009-08-04 22:39:05 +02:00
define float @test2(float* %a) {
entry:
%0 = load float* %a, align 4 ; <float> [#uses=2]
%1 = fmul float -1.000000e+00, %0 ; <float> [#uses=2]
%2 = fpext float %1 to double ; <double> [#uses=1]
%3 = fcmp olt double %2, 1.234000e+00 ; <i1> [#uses=1]
%retval = select i1 %3, float %1, float %0 ; <float> [#uses=1]
ret float %retval
}
Convert ARM tests to FileCheck for PR5307. llvm-svn: 89593
2009-11-22 15:23:33 +01:00
; VFP2: test2:
Convert -enable-sched-cycles and -enable-sched-hazard to -disable flags. They are still not enable in this revision. Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with the scheduler's model of operand latency in the selection DAG. Generalized unit tests to work with sched-cycles. llvm-svn: 123969
2011-01-21 06:51:33 +01:00
; VFP2: vneg.f32 s{{.*}}, s{{.*}}
Convert ARM tests to FileCheck for PR5307. llvm-svn: 89593
2009-11-22 15:23:33 +01:00
; NFP1: test2:
Convert -enable-sched-cycles and -enable-sched-hazard to -disable flags. They are still not enable in this revision. Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with the scheduler's model of operand latency in the selection DAG. Generalized unit tests to work with sched-cycles. llvm-svn: 123969
2011-01-21 06:51:33 +01:00
; NFP1: vneg.f32 d{{.*}}, d{{.*}}
Convert ARM tests to FileCheck for PR5307. llvm-svn: 89593
2009-11-22 15:23:33 +01:00
; NFP0: test2:
Convert -enable-sched-cycles and -enable-sched-hazard to -disable flags. They are still not enable in this revision. Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with the scheduler's model of operand latency in the selection DAG. Generalized unit tests to work with sched-cycles. llvm-svn: 123969
2011-01-21 06:51:33 +01:00
; NFP0: vneg.f32 s{{.*}}, s{{.*}}
Convert ARM tests to FileCheck for PR5307. llvm-svn: 89593
2009-11-22 15:23:33 +01:00
; CORTEXA8: test2:
Avoid NEON SP-FP unless unsafe-math or Darwin NEON is not IEEE 754 compliant, so we should avoid lowering single-precision floating point operations with NEON unless unsafe-math is turned on. The equivalent VFP instructions are IEEE 754 compliant, but in some cores they're much slower, so some archs/OSs might still request it to be on by default, such as Swift and Darwin. llvm-svn: 177651
2013-03-21 19:47:47 +01:00
; CORTEXA8: vneg.f32 s{{.*}}, s{{.*}}
; CORTEXA8U: test2:
; CORTEXA8U: vneg.f32 d{{.*}}, d{{.*}}
Convert ARM tests to FileCheck for PR5307. llvm-svn: 89593
2009-11-22 15:23:33 +01:00
; CORTEXA9: test2:
Convert -enable-sched-cycles and -enable-sched-hazard to -disable flags. They are still not enable in this revision. Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with the scheduler's model of operand latency in the selection DAG. Generalized unit tests to work with sched-cycles. llvm-svn: 123969
2011-01-21 06:51:33 +01:00
; CORTEXA9: vneg.f32 s{{.*}}, s{{.*}}
Convert ARM tests to FileCheck for PR5307. llvm-svn: 89593
2009-11-22 15:23:33 +01:00
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