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llvm-mirror/test/CodeGen/ARM/neon_div.ll

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ARM scheduling fix: compute predicated implicit use properly. Minor drive by fix to cleanup latency computation. Calling getOperandLatency with a deliberately incorrect operand index does not give you the latency you want. llvm-svn: 158959
2012-06-22 04:50:31 +02:00
; RUN: llc < %s -march=arm -mattr=+neon -pre-RA-sched=source -disable-post-ra | FileCheck %s
Implement sdiv & udiv for <4 x i16> and <8 x i8> NEON vector types. This avoids moving each element to the integer register file and calling __divsi3 etc. on it. llvm-svn: 125402
2011-02-11 21:53:29 +01:00
define <8 x i8> @sdivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
;CHECK: vrecpe.f32
;CHECK: vmovn.i32
ARM scheduling fix: compute predicated implicit use properly. Minor drive by fix to cleanup latency computation. Calling getOperandLatency with a deliberately incorrect operand index does not give you the latency you want. llvm-svn: 158959
2012-06-22 04:50:31 +02:00
;CHECK: vrecpe.f32
Implement sdiv & udiv for <4 x i16> and <8 x i8> NEON vector types. This avoids moving each element to the integer register file and calling __divsi3 etc. on it. llvm-svn: 125402
2011-02-11 21:53:29 +01:00
;CHECK: vmovn.i32
;CHECK: vmovn.i16
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
%tmp3 = sdiv <8 x i8> %tmp1, %tmp2
ret <8 x i8> %tmp3
}
define <8 x i8> @udivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
;CHECK: vrecpe.f32
;CHECK: vrecps.f32
ARM scheduling fix: compute predicated implicit use properly. Minor drive by fix to cleanup latency computation. Calling getOperandLatency with a deliberately incorrect operand index does not give you the latency you want. llvm-svn: 158959
2012-06-22 04:50:31 +02:00
;CHECK: vmovn.i32
Implement sdiv & udiv for <4 x i16> and <8 x i8> NEON vector types. This avoids moving each element to the integer register file and calling __divsi3 etc. on it. llvm-svn: 125402
2011-02-11 21:53:29 +01:00
;CHECK: vrecpe.f32
;CHECK: vrecps.f32
;CHECK: vmovn.i32
;CHECK: vqmovun.s16
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
%tmp3 = udiv <8 x i8> %tmp1, %tmp2
ret <8 x i8> %tmp3
}
define <4 x i16> @sdivi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
;CHECK: vrecpe.f32
;CHECK: vrecps.f32
;CHECK: vmovn.i32
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
%tmp3 = sdiv <4 x i16> %tmp1, %tmp2
ret <4 x i16> %tmp3
}
define <4 x i16> @udivi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
;CHECK: vrecpe.f32
;CHECK: vrecps.f32
;CHECK: vrecps.f32
;CHECK: vmovn.i32
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
%tmp3 = udiv <4 x i16> %tmp1, %tmp2
ret <4 x i16> %tmp3
}
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