2012-02-18 13:03:15 +01:00
|
|
|
//===-- ARMBaseRegisterInfo.h - ARM Register Information Impl ---*- C++ -*-===//
|
2009-07-08 19:28:55 +02:00
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
// This file contains the base ARM implementation of TargetRegisterInfo class.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
#ifndef ARMBASEREGISTERINFO_H
|
|
|
|
#define ARMBASEREGISTERINFO_H
|
|
|
|
|
|
|
|
#include "ARM.h"
|
|
|
|
#include "llvm/Target/TargetRegisterInfo.h"
|
2011-06-27 20:32:37 +02:00
|
|
|
|
|
|
|
#define GET_REGINFO_HEADER
|
|
|
|
#include "ARMGenRegisterInfo.inc"
|
2009-07-08 19:28:55 +02:00
|
|
|
|
|
|
|
namespace llvm {
|
|
|
|
class ARMSubtarget;
|
2009-07-08 20:31:39 +02:00
|
|
|
class ARMBaseInstrInfo;
|
2009-07-08 19:28:55 +02:00
|
|
|
class Type;
|
|
|
|
|
|
|
|
/// Register allocation hints.
|
|
|
|
namespace ARMRI {
|
|
|
|
enum {
|
|
|
|
RegPairOdd = 1,
|
|
|
|
RegPairEven = 2
|
|
|
|
};
|
|
|
|
}
|
|
|
|
|
2010-11-18 20:40:05 +01:00
|
|
|
/// isARMArea1Register - Returns true if the register is a low register (r0-r7)
|
|
|
|
/// or a stack/pc register that we should push/pop.
|
2012-01-04 02:55:04 +01:00
|
|
|
static inline bool isARMArea1Register(unsigned Reg, bool isIOS) {
|
2010-11-18 20:40:05 +01:00
|
|
|
using namespace ARM;
|
|
|
|
switch (Reg) {
|
|
|
|
case R0: case R1: case R2: case R3:
|
|
|
|
case R4: case R5: case R6: case R7:
|
|
|
|
case LR: case SP: case PC:
|
|
|
|
return true;
|
|
|
|
case R8: case R9: case R10: case R11:
|
2012-01-04 02:55:04 +01:00
|
|
|
// For iOS we want r7 and lr to be next to each other.
|
|
|
|
return !isIOS;
|
2010-11-18 20:40:05 +01:00
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-01-04 02:55:04 +01:00
|
|
|
static inline bool isARMArea2Register(unsigned Reg, bool isIOS) {
|
2010-11-18 20:40:05 +01:00
|
|
|
using namespace ARM;
|
|
|
|
switch (Reg) {
|
|
|
|
case R8: case R9: case R10: case R11:
|
2012-01-04 02:55:04 +01:00
|
|
|
// iOS has this second area.
|
|
|
|
return isIOS;
|
2010-11-18 20:40:05 +01:00
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-01-04 02:55:04 +01:00
|
|
|
static inline bool isARMArea3Register(unsigned Reg, bool isIOS) {
|
2010-11-18 20:40:05 +01:00
|
|
|
using namespace ARM;
|
|
|
|
switch (Reg) {
|
|
|
|
case D15: case D14: case D13: case D12:
|
|
|
|
case D11: case D10: case D9: case D8:
|
|
|
|
return true;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-07-20 23:17:29 +02:00
|
|
|
class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
|
2009-07-08 19:28:55 +02:00
|
|
|
protected:
|
|
|
|
const ARMSubtarget &STI;
|
|
|
|
|
|
|
|
/// FramePtr - ARM physical register used as frame ptr.
|
|
|
|
unsigned FramePtr;
|
|
|
|
|
2010-09-03 20:37:12 +02:00
|
|
|
/// BasePtr - ARM physical register used as a base ptr in complex stack
|
|
|
|
/// frames. I.e., when we need a 3rd base, not just SP and FP, due to
|
|
|
|
/// variable size stack objects.
|
|
|
|
unsigned BasePtr;
|
|
|
|
|
2009-07-08 20:31:39 +02:00
|
|
|
// Can be only subclassed.
|
2013-06-07 07:54:19 +02:00
|
|
|
explicit ARMBaseRegisterInfo(const ARMSubtarget &STI);
|
2009-07-08 20:31:39 +02:00
|
|
|
|
2009-07-08 22:28:28 +02:00
|
|
|
// Return the opcode that implements 'Op', or 0 if no opcode
|
|
|
|
unsigned getOpcode(int Op) const;
|
|
|
|
|
2009-07-08 20:31:39 +02:00
|
|
|
public:
|
2009-07-08 19:28:55 +02:00
|
|
|
/// Code Generation virtual methods...
|
2012-03-04 04:33:22 +01:00
|
|
|
const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
|
2012-01-18 00:09:00 +01:00
|
|
|
const uint32_t *getCallPreservedMask(CallingConv::ID) const;
|
2012-11-07 00:05:24 +01:00
|
|
|
const uint32_t *getNoPreservedMask() const;
|
2009-07-08 19:28:55 +02:00
|
|
|
|
2013-06-27 00:27:50 +02:00
|
|
|
/// getThisReturnPreservedMask - Returns a call preserved mask specific to the
|
|
|
|
/// case that 'returned' is on an i32 first argument if the calling convention
|
|
|
|
/// is one that can (partially) model this attribute with a preserved mask
|
|
|
|
/// (i.e. it is a calling convention that uses the same register for the first
|
|
|
|
/// i32 argument and an i32 return value)
|
|
|
|
///
|
|
|
|
/// Should return NULL in the case that the calling convention does not have
|
|
|
|
/// this property
|
2013-06-26 23:42:14 +02:00
|
|
|
const uint32_t *getThisReturnPreservedMask(CallingConv::ID) const;
|
|
|
|
|
2009-07-08 19:28:55 +02:00
|
|
|
BitVector getReservedRegs(const MachineFunction &MF) const;
|
|
|
|
|
2012-05-08 00:10:26 +02:00
|
|
|
const TargetRegisterClass*
|
|
|
|
getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const;
|
2011-08-30 03:34:54 +02:00
|
|
|
const TargetRegisterClass*
|
|
|
|
getCrossCopyRegClass(const TargetRegisterClass *RC) const;
|
2009-07-08 19:28:55 +02:00
|
|
|
|
2011-04-26 20:52:33 +02:00
|
|
|
const TargetRegisterClass*
|
|
|
|
getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
|
|
|
|
|
2011-03-07 22:56:36 +01:00
|
|
|
unsigned getRegPressureLimit(const TargetRegisterClass *RC,
|
|
|
|
MachineFunction &MF) const;
|
|
|
|
|
2012-12-03 23:35:35 +01:00
|
|
|
void getRegAllocationHints(unsigned VirtReg,
|
|
|
|
ArrayRef<MCPhysReg> Order,
|
|
|
|
SmallVectorImpl<MCPhysReg> &Hints,
|
|
|
|
const MachineFunction &MF,
|
|
|
|
const VirtRegMap *VRM) const;
|
|
|
|
|
2009-07-08 19:28:55 +02:00
|
|
|
void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
|
|
|
|
MachineFunction &MF) const;
|
|
|
|
|
2011-04-19 20:11:45 +02:00
|
|
|
virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const;
|
|
|
|
|
2010-09-03 20:37:12 +02:00
|
|
|
bool hasBasePointer(const MachineFunction &MF) const;
|
2009-08-14 22:48:13 +02:00
|
|
|
|
2010-01-19 19:31:11 +01:00
|
|
|
bool canRealignStack(const MachineFunction &MF) const;
|
2009-10-27 23:45:39 +01:00
|
|
|
bool needsStackRealignment(const MachineFunction &MF) const;
|
2010-08-26 23:56:30 +02:00
|
|
|
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const;
|
2010-08-24 23:19:33 +02:00
|
|
|
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const;
|
2010-12-18 00:09:14 +01:00
|
|
|
void materializeFrameBaseRegister(MachineBasicBlock *MBB,
|
2010-08-20 01:52:25 +02:00
|
|
|
unsigned BaseReg, int FrameIdx,
|
|
|
|
int64_t Offset) const;
|
2010-08-18 00:41:55 +02:00
|
|
|
void resolveFrameIndex(MachineBasicBlock::iterator I,
|
|
|
|
unsigned BaseReg, int64_t Offset) const;
|
2010-08-20 01:52:25 +02:00
|
|
|
bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const;
|
2009-10-27 23:45:39 +01:00
|
|
|
|
2009-08-15 04:05:35 +02:00
|
|
|
bool cannotEliminateFrame(const MachineFunction &MF) const;
|
2009-07-08 19:28:55 +02:00
|
|
|
|
|
|
|
// Debug information queries.
|
2009-11-12 22:00:03 +01:00
|
|
|
unsigned getFrameRegister(const MachineFunction &MF) const;
|
2010-11-15 02:45:44 +01:00
|
|
|
unsigned getBaseRegister() const { return BasePtr; }
|
2009-07-08 19:28:55 +02:00
|
|
|
|
|
|
|
// Exception handling queries.
|
|
|
|
unsigned getEHExceptionRegister() const;
|
|
|
|
unsigned getEHHandlerRegister() const;
|
|
|
|
|
|
|
|
bool isLowRegister(unsigned Reg) const;
|
|
|
|
|
2009-07-08 20:31:39 +02:00
|
|
|
|
|
|
|
/// emitLoadConstPool - Emits a load from constpool to materialize the
|
|
|
|
/// specified immediate.
|
|
|
|
virtual void emitLoadConstPool(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator &MBBI,
|
2009-07-08 22:28:28 +02:00
|
|
|
DebugLoc dl,
|
2009-07-16 11:20:10 +02:00
|
|
|
unsigned DestReg, unsigned SubIdx,
|
|
|
|
int Val,
|
2009-07-08 20:31:39 +02:00
|
|
|
ARMCC::CondCodes Pred = ARMCC::AL,
|
2011-03-05 19:43:50 +01:00
|
|
|
unsigned PredReg = 0,
|
|
|
|
unsigned MIFlags = MachineInstr::NoFlags)const;
|
2009-07-08 20:31:39 +02:00
|
|
|
|
|
|
|
/// Code Generation virtual methods...
|
|
|
|
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
|
|
|
|
|
2012-04-23 23:39:35 +02:00
|
|
|
virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const;
|
|
|
|
|
2009-10-20 03:26:58 +02:00
|
|
|
virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
|
2010-08-24 21:05:43 +02:00
|
|
|
|
|
|
|
virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const;
|
2009-10-20 03:26:58 +02:00
|
|
|
|
2010-08-27 01:32:16 +02:00
|
|
|
virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
|
2013-01-31 21:02:54 +01:00
|
|
|
int SPAdj, unsigned FIOperandNum,
|
|
|
|
RegScavenger *RS = NULL) const;
|
2009-07-08 19:28:55 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
} // end namespace llvm
|
|
|
|
|
|
|
|
#endif
|