llvm-mirror/test/CodeGen/Thumb/barrier.ll

; RUN: llc < %s -march=thumb -mattr=+v6      | FileCheck %s -check-prefix=V6
; RUN: llc < %s -march=thumb -mcpu=cortex-m0 | FileCheck %s -check-prefix=M0

declare void @llvm.memory.barrier( i1 , i1 , i1 , i1 , i1 )

define void @t1() {
; V6: t1:
; V6: blx {{_*}}sync_synchronize

; M0: t1:
; M0: dsb
  call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 true, i1 true )
  ret void
}

define void @t2() {
; V6: t2:
; V6: blx {{_*}}sync_synchronize

; M0: t2:
; M0: dmb
  call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 true, i1 false )
  ret void
}
Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bit instructions: dmb, dsb, isb, msr, and mrs. llvm-svn: 110786 2010-08-11 08:30:38 +02:00			`; RUN: llc < %s -march=thumb -mattr=+v6 \| FileCheck %s -check-prefix=V6`
			`; RUN: llc < %s -march=thumb -mcpu=cortex-m0 \| FileCheck %s -check-prefix=M0`
- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the memory and synchronization barrier dmb and dsb instructions. - Change instruction names to something more sensible (matching name of actual instructions). - Added tests for memory barrier codegen. llvm-svn: 110785 2010-08-11 08:22:01 +02:00
			`declare void @llvm.memory.barrier( i1 , i1 , i1 , i1 , i1 )`

			`define void @t1() {`
Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bit instructions: dmb, dsb, isb, msr, and mrs. llvm-svn: 110786 2010-08-11 08:30:38 +02:00			`; V6: t1:`
			`; V6: blx {{_*}}sync_synchronize`

			`; M0: t1:`
			`; M0: dsb`
- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the memory and synchronization barrier dmb and dsb instructions. - Change instruction names to something more sensible (matching name of actual instructions). - Added tests for memory barrier codegen. llvm-svn: 110785 2010-08-11 08:22:01 +02:00			`call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 true, i1 true )`
			`ret void`
			`}`

			`define void @t2() {`
Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bit instructions: dmb, dsb, isb, msr, and mrs. llvm-svn: 110786 2010-08-11 08:30:38 +02:00			`; V6: t2:`
			`; V6: blx {{_*}}sync_synchronize`

			`; M0: t2:`
			`; M0: dmb`
- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the memory and synchronization barrier dmb and dsb instructions. - Change instruction names to something more sensible (matching name of actual instructions). - Added tests for memory barrier codegen. llvm-svn: 110785 2010-08-11 08:22:01 +02:00			`call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 true, i1 false )`
			`ret void`
			`}`