llvm-mirror/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

// WebAssemblyInstrSIMD.td - WebAssembly SIMD codegen support -*- tablegen -*-//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
///
/// \file
/// \brief WebAssembly SIMD operand code-gen constructs.
///
//===----------------------------------------------------------------------===//

// TODO: Implement SIMD instructions.
// Note: use Requires<[HasSIMD128]>.
[WebAssembly] Initial WebAssembly backend This WebAssembly backend is just a skeleton at this time and is not yet functional. llvm-svn: 241022 2015-06-30 01:51:55 +02:00			`// WebAssemblyInstrSIMD.td - WebAssembly SIMD codegen support -- tablegen --//`
			`//`
			`// The LLVM Compiler Infrastructure`
			`//`
			`// This file is distributed under the University of Illinois Open Source`
			`// License. See LICENSE.TXT for details.`
			`//`
			`//===----------------------------------------------------------------------===//`
WebAssembly: basic instructions todo, and basic register info. Summary: This code is based on AArch64 for modern backend good practice, and NVPTX for virtual ISA concerns. Reviewers: sunfish Subscribers: aemerson, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11070 llvm-svn: 241923 2015-07-10 20:23:10 +02:00			`///`
			`/// \file`
			`/// \brief WebAssembly SIMD operand code-gen constructs.`
			`///`
[WebAssembly] Initial WebAssembly backend This WebAssembly backend is just a skeleton at this time and is not yet functional. llvm-svn: 241022 2015-06-30 01:51:55 +02:00			`//===----------------------------------------------------------------------===//`

			`// TODO: Implement SIMD instructions.`
WebAssembly: start instructions Summary: * Add 64-bit address space feature. * Rename SIMD feature to SIMD128. * Handle single-thread model with an IR pass (same way ARM does). * Rename generic processor to MVP, to follow design's lead. * Add bleeding-edge processors, with all features included. * Fix a few DEBUG_TYPE to match other backends. Test Plan: ninja check Reviewers: sunfish Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D10880 llvm-svn: 241211 2015-07-02 01:41:25 +02:00			`// Note: use Requires<[HasSIMD128]>.`