llvm-mirror/test/CodeGen/ARM/carry.ll

; RUN: llc < %s -march=arm | FileCheck %s

define i64 @f1(i64 %a, i64 %b) {
; CHECK: f1:
; CHECK: subs r
; CHECK: sbc r
entry:
	%tmp = sub i64 %a, %b
	ret i64 %tmp
}

define i64 @f2(i64 %a, i64 %b) {
; CHECK: f2:
; CHECK: adc r
; CHECK: subs r
; CHECK: sbc r
entry:
        %tmp1 = shl i64 %a, 1
	%tmp2 = sub i64 %tmp1, %b
	ret i64 %tmp2
}
Fix some more failures by converting to FileCheck. llvm-svn: 85207 2009-10-27 06:50:28 +01:00			`; RUN: llc < %s -march=arm \| FileCheck %s`
ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS. llvm-svn: 74200 2009-06-25 22:59:23 +02:00
			`define i64 @f1(i64 %a, i64 %b) {`
Fix some more failures by converting to FileCheck. llvm-svn: 85207 2009-10-27 06:50:28 +01:00			`; CHECK: f1:`
			`; CHECK: subs r`
			`; CHECK: sbc r`
ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS. llvm-svn: 74200 2009-06-25 22:59:23 +02:00			`entry:`
			`%tmp = sub i64 %a, %b`
			`ret i64 %tmp`
			`}`

			`define i64 @f2(i64 %a, i64 %b) {`
Fix some more failures by converting to FileCheck. llvm-svn: 85207 2009-10-27 06:50:28 +01:00			`; CHECK: f2:`
			`; CHECK: adc r`
			`; CHECK: subs r`
			`; CHECK: sbc r`
ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS. llvm-svn: 74200 2009-06-25 22:59:23 +02:00			`entry:`
			`%tmp1 = shl i64 %a, 1`
			`%tmp2 = sub i64 %tmp1, %b`
			`ret i64 %tmp2`
			`}`