RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-22 18:54:02 +01:00
Code Issues Projects Releases Wiki Activity
bedf13b1a7
llvm-mirror/test/CodeGen/AArch64/fast-isel-sp-adjust.ll

289 lines
14 KiB
LLVM
Raw Normal View History

[AArch64][GlobalISel] Enable GlobalISel at -O0 by default Tests updated to explicitly use fast-isel at -O0 instead of implicitly. This change also allows an explicit -fast-isel option to override an implicitly enabled global-isel. Otherwise -fast-isel would have no effect at -O0. Differential Revision: https://reviews.llvm.org/D41362 llvm-svn: 321655
2018-01-02 17:30:47 +01:00
; RUN: llc -O0 -fast-isel -mtriple=aarch64-apple-ios -o - %s | FileCheck %s
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" This reverts commit 80a34ae31125aa46dcad47162ba45b152aed968d with fixes. Previously, since bots turning on EXPENSIVE_CHECKS are essentially turning on MachineVerifierPass by default on X86 and the fact that inline-asm-avx-v-constraint-32bit.ll and inline-asm-avx512vl-v-constraint-32bit.ll are not expected to generate functioning machine code, this would go down to `report_fatal_error` in MachineVerifierPass. Here passing `-verify-machineinstrs=0` to make the intent explicit.
2020-02-12 08:01:35 +01:00
; RUN: not --crash llc -O0 -mtriple=aarch64-apple-ios -o /dev/null -fast-isel -fast-isel-abort=3 %s 2> %t
AArch64: don't try to emit an add (shifted reg) for SP. The "Add/sub (shifted reg)" instructions use the 31 encoding for xzr and wzr rather than the SP, so we need to use different variants. Situations where this actually comes up are rare enough (see test-case) that I think falling back to DAG is fine. llvm-svn: 305230
2017-06-12 22:49:53 +02:00
; RUN: FileCheck %s --check-prefix=CHECK-ERRORS < %t
; The issue here is that FastISel cannot emit an ADDrr where one of the inputs
; is SP. This only ever crops up with function calls, and then only if the
; argument is at an offset > 2^12 * size from SP.
; If FastISel ever starts coping with this and emits an "add xD, sp, xM" it's
; critical to check the encoding as well as the textual assembly. An ADDXrs with
; SP as an operand will still print with SP, but will actually mean XZR.
; CHECK-ERRORS: LLVM ERROR: FastISel missed call
; CHECK-LABEL: foo:
Relanding r368987 [AArch64] Change location of frame-record within callee-save area. Changes: There was a condition for `!NeedsFrameRecord` missing in the assert. The assert in question has changed to: + assert((!RPI.isPaired() || !NeedsFrameRecord || RPI.Reg2 != AArch64::FP || + RPI.Reg1 == AArch64::LR) && + "FrameRecord must be allocated together with LR"); This addresses PR43016. llvm-svn: 369122
2019-08-16 17:42:28 +02:00
; CHECK: sub
AArch64: don't try to emit an add (shifted reg) for SP. The "Add/sub (shifted reg)" instructions use the 31 encoding for xzr and wzr rather than the SP, so we need to use different variants. Situations where this actually comes up are rare enough (see test-case) that I think falling back to DAG is fine. llvm-svn: 305230
2017-06-12 22:49:53 +02:00
; CHECK-DAG: mov x[[SP:[0-9]+]], sp
Reapply "RegAllocFast: Record internal state based on register units" The regressions this caused should be fixed when https://reviews.llvm.org/D52010 is applied. This reverts commit a21387c65470417c58021f8d3194a4510bb64f46.
2020-09-15 15:16:14 +02:00
; CHECK-DAG: mov w[[OFFSET:[0-9]+]], #4104
AArch64: don't try to emit an add (shifted reg) for SP. The "Add/sub (shifted reg)" instructions use the 31 encoding for xzr and wzr rather than the SP, so we need to use different variants. Situations where this actually comes up are rare enough (see test-case) that I think falling back to DAG is fine. llvm-svn: 305230
2017-06-12 22:49:53 +02:00
; CHECK: strb w0, [x[[SP]], x[[OFFSET]]]
define void @foo(i8 %in) {
call void @bar(i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef, ; All regs gone.
i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 32
i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 64
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 128
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 256
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 512
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 1024
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 2048
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef,
i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 4096
i64 undef, ; sp + 4104 (i.e. not uimm12 or uimm12 << 12).
i8 %in)
ret void
}
declare void @bar(i64, i64, i64, i64,
i64, i64, i64, i64, ; All regs gone.
i64, i64, i64, i64, ; sp + 32
i64, i64, i64, i64, ; sp + 64
i64, i64, i64, i64,
i64, i64, i64, i64, ; sp + 128
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64, ; sp + 256
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64, ; sp + 512
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64, ; sp + 1024
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64, ; sp + 2048
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64,
i64, i64, i64, i64, ; sp + 4096
i64,
i8)
Reference in New Issue Copy Permalink