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llvm-mirror/lib/Target/AVR/CMakeLists.txt

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Add AVR.td and AVRRegisterInfo.td Summary: This adds the core AVR TableGen file, along with the register descriptions. Lines in AVR.td which require other TableGen files which haven't been committed yet are commented out. This is a fairly trivial patch, and should only require a quick review. I kept the line width smaller than 80 columns, but there are a few exceptions because I'm not sure how to split a string over several lines. Reviewers: stoklund Subscribers: dylanmckay, agnat Differential Revision: http://reviews.llvm.org/D14684 llvm-svn: 256120
2015-12-20 13:16:20 +01:00
set(LLVM_TARGET_DEFINITIONS AVR.td)
Add AVR backend skeleton This adds part of the target info code, and adds modifications to the build scripts so that AVR is recognized a supported, experimental backend. It does not include any AVR-specific code, just the bare sources required for a backend to exist. From D14039. llvm-svn: 252865
2015-11-12 10:26:44 +01:00
[AVR] Add assembly parser Summary: This patch adds the AVRAsmParser library. Reviewers: arsenm, kparzysz Subscribers: wdng, beanz, mgorny, kparzysz, simoncook, jtbandes, llvm-commits Differential Revision: https://reviews.llvm.org/D20046 llvm-svn: 282584
2016-09-28 15:02:57 +02:00
tablegen(LLVM AVRGenAsmMatcher.inc -gen-asm-matcher)
[AVR] Enable generation of the TableGen assembly writer tables This also changes the order of the statements in CMakeLists.txt to be alphabetical. llvm-svn: 283711
2016-10-10 03:28:45 +02:00
tablegen(LLVM AVRGenAsmWriter.inc -gen-asm-writer)
[AVR] Added AVRCallingConv.td llvm-svn: 256130
2015-12-21 00:17:44 +01:00
tablegen(LLVM AVRGenCallingConv.inc -gen-callingconv)
[AVR] Add AVRISelDAGToDAG.cpp Summary: This pulls the AVR instruction selector in-tree. Reviewers: arsenm, kparzysz Subscribers: llvm-commits, wdng, beanz, japaric, mgorny Differential Revision: https://reviews.llvm.org/D25278 llvm-svn: 285270
2016-10-27 09:03:47 +02:00
tablegen(LLVM AVRGenDAGISel.inc -gen-dag-isel)
[AVR] Add the machine code disassembler This adds a super basic implementation of a machine code disassembler. It doesn't support any operands with custom encoding. llvm-svn: 284930
2016-10-23 01:57:59 +02:00
tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler)
[AVR] Enable generation of the TableGen assembly writer tables This also changes the order of the statements in CMakeLists.txt to be alphabetical. llvm-svn: 283711
2016-10-10 03:28:45 +02:00
tablegen(LLVM AVRGenInstrInfo.inc -gen-instr-info)
Remove duplicate tablegen lines from AVR target. They were added in r285274, in what looks like a merge mishap. AVRGenMCCodeEmitter.inc is the only non-dupe tablegen invocation added in that revision. Also sort the tablegen lines to make this easier to spot in the future. llvm-svn: 329178
2018-04-04 14:27:43 +02:00
tablegen(LLVM AVRGenMCCodeEmitter.inc -gen-emitter)
[AVR] Enable generation of the TableGen assembly writer tables This also changes the order of the statements in CMakeLists.txt to be alphabetical. llvm-svn: 283711
2016-10-10 03:28:45 +02:00
tablegen(LLVM AVRGenRegisterInfo.inc -gen-register-info)
[AVR] Add a majority of the backend code Summary: This adds the majority of the AVR backend. Reviewers: hfinkel, dsanders, vkalintiris, arsenm Subscribers: dylanmckay Differential Revision: http://reviews.llvm.org/D17906 llvm-svn: 268722
2016-05-06 12:12:31 +02:00
tablegen(LLVM AVRGenSubtargetInfo.inc -gen-subtarget)
Remove duplicate tablegen lines from AVR target. They were added in r285274, in what looks like a merge mishap. AVRGenMCCodeEmitter.inc is the only non-dupe tablegen invocation added in that revision. Also sort the tablegen lines to make this easier to spot in the future. llvm-svn: 329178
2018-04-04 14:27:43 +02:00
Add AVR.td and AVRRegisterInfo.td Summary: This adds the core AVR TableGen file, along with the register descriptions. Lines in AVR.td which require other TableGen files which haven't been committed yet are commented out. This is a fairly trivial patch, and should only require a quick review. I kept the line width smaller than 80 columns, but there are a few exceptions because I'm not sure how to split a string over several lines. Reviewers: stoklund Subscribers: dylanmckay, agnat Differential Revision: http://reviews.llvm.org/D14684 llvm-svn: 256120
2015-12-20 13:16:20 +01:00
add_public_tablegen_target(AVRCommonTableGen)
Add AVR backend skeleton This adds part of the target info code, and adds modifications to the build scripts so that AVR is recognized a supported, experimental backend. It does not include any AVR-specific code, just the bare sources required for a backend to exist. From D14039. llvm-svn: 252865
2015-11-12 10:26:44 +01:00
add_llvm_target(AVRCodeGen
[AVR] Add the assembly printer Summary: This adds the AVRAsmPrinter class. Reviewers: arsenm, kparzysz Subscribers: llvm-commits, wdng, beanz, japaric, mgorny Differential Revision: https://reviews.llvm.org/D25271 llvm-svn: 283623
2016-10-08 02:02:36 +02:00
AVRAsmPrinter.cpp
[AVR] Add the pseudo instruction expansion pass Summary: A lot of the pseudo instructions are required because LLVM assumes that all integers of the same size as the pointer size are legal. This means that it will not currently expand 16-bit instructions to their 8-bit variants because it thinks 16-bit types are legal for the operations. This also adds all of the CodeGen tests that required the pass to run. Reviewers: arsenm, kparzysz Subscribers: wdng, mgorny, modocache, llvm-commits Differential Revision: https://reviews.llvm.org/D26577 llvm-svn: 287162
2016-11-16 22:58:04 +01:00
AVRExpandPseudoInsts.cpp
[AVR] Add the AVR frame lowering code Summary: This allows AVR to lower frames into assembly code. Reviewers: arsenm, kparzysz Subscribers: japaric, wdng, beanz, mgorny Differential Revision: https://reviews.llvm.org/D25032 llvm-svn: 283311
2016-10-05 13:48:56 +02:00
AVRFrameLowering.cpp
[AVR] Add missing CMake dependencies llvm-svn: 269901
2016-05-18 13:11:51 +02:00
AVRInstrInfo.cpp
[AVR] Add AVRISelDAGToDAG.cpp Summary: This pulls the AVR instruction selector in-tree. Reviewers: arsenm, kparzysz Subscribers: llvm-commits, wdng, beanz, japaric, mgorny Differential Revision: https://reviews.llvm.org/D25278 llvm-svn: 285270
2016-10-27 09:03:47 +02:00
AVRISelDAGToDAG.cpp
[AVR] Add instruction selection lowering code Summary: This adds AVRISelLowering.cpp Reviewers: arsenm, kparzysz Subscribers: llvm-commits, modocache, japaric, wdng, beanz, mgorny Differential Revision: https://reviews.llvm.org/D25034 llvm-svn: 285790
2016-11-02 07:47:40 +01:00
AVRISelLowering.cpp
[AVR] Add the AVRMCInstLower class Summary: This class deals with the lowering of CodeGen `MachineInstr` objects to MC `MCInst` objects. Reviewers: kparzysz, arsenm Subscribers: wdng, beanz, japaric, mgorny Differential Revision: https://reviews.llvm.org/D25269 llvm-svn: 283522
2016-10-07 08:13:09 +02:00
AVRMCInstLower.cpp
[AVR] Add an 'relax memory operation' pass Summary: This pass will be used to relax instructions which use out of bounds memory accesses to equivalent operations that can work with the addresses. The pass currently implements relaxation for the STDWPtrQRr instruction. Without this pass, an assertion error would be hit in the pseudo expansion pass. In the future, we will need to add more instructions to this pass. We can do that on a case-by-case basic. Reviewers: arsenm, kparzysz Subscribers: wdng, llvm-commits, mgorny Differential Revision: https://reviews.llvm.org/D27650 llvm-svn: 289517
2016-12-13 06:53:14 +01:00
AVRRelaxMemOperations.cpp
[AVR] Add missing CMake dependencies llvm-svn: 269901
2016-05-18 13:11:51 +02:00
AVRRegisterInfo.cpp
AVRSubtarget.cpp
AVRTargetMachine.cpp
AVRTargetObjectFile.cpp
Add AVR backend skeleton This adds part of the target info code, and adds modifications to the build scripts so that AVR is recognized a supported, experimental backend. It does not include any AVR-specific code, just the bare sources required for a backend to exist. From D14039. llvm-svn: 252865
2015-11-12 10:26:44 +01:00
[CMake] NFC. Updating CMake dependency specifications This patch updates a bunch of places where add_dependencies was being explicitly called to add dependencies on intrinsics_gen to instead use the DEPENDS named parameter. This cleanup is needed for a patch I'm working on to add a dependency debugging mode to the build system. llvm-svn: 287206
2016-11-17 05:36:50 +01:00
DEPENDS
intrinsics_gen
)
Add AVR backend skeleton This adds part of the target info code, and adds modifications to the build scripts so that AVR is recognized a supported, experimental backend. It does not include any AVR-specific code, just the bare sources required for a backend to exist. From D14039. llvm-svn: 252865
2015-11-12 10:26:44 +01:00
[AVR] Add the assembly instruction printer Summary: This change adds the AVR assembly instruction printer. No tests are included in this patch. I have left them downstream so we can add them once `llc` successfully runs (there's very few components left to upstream until this). Reviewers: arsenm, kparzysz Subscribers: wdng, beanz, mgorny Differential Revision: https://reviews.llvm.org/D25028 llvm-svn: 282854
2016-09-30 16:01:50 +02:00
add_subdirectory(AsmParser)
[AVR] Compile the disassembler This also updates references of 'TheAVRTarget' to the new 'getTheAVRTarget()' method. llvm-svn: 285272
2016-10-27 10:09:15 +02:00
add_subdirectory(Disassembler)
[AVR] Fix header files in MCTargetDesc Everything now compiles successfully, but there are still undefined references. llvm-svn: 270298
2016-05-21 02:35:07 +02:00
add_subdirectory(MCTargetDesc)
Add AVR backend skeleton This adds part of the target info code, and adds modifications to the build scripts so that AVR is recognized a supported, experimental backend. It does not include any AVR-specific code, just the bare sources required for a backend to exist. From D14039. llvm-svn: 252865
2015-11-12 10:26:44 +01:00
add_subdirectory(TargetInfo)
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