2012-02-18 13:03:15 +01:00
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//===-- MSP430InstrInfo.h - MSP430 Instruction Information ------*- C++ -*-===//
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2009-05-03 14:57:15 +02:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the MSP430 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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2014-08-13 18:26:38 +02:00
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#ifndef LLVM_LIB_TARGET_MSP430_MSP430INSTRINFO_H
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#define LLVM_LIB_TARGET_MSP430_MSP430INSTRINFO_H
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2009-05-03 14:57:15 +02:00
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#include "MSP430RegisterInfo.h"
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2012-03-17 19:46:09 +01:00
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#include "llvm/Target/TargetInstrInfo.h"
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2009-05-03 14:57:15 +02:00
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2011-07-01 19:57:27 +02:00
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#define GET_INSTRINFO_HEADER
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#include "MSP430GenInstrInfo.inc"
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2009-05-03 14:57:15 +02:00
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namespace llvm {
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2014-06-27 03:14:50 +02:00
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class MSP430Subtarget;
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2009-05-03 14:57:15 +02:00
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2010-01-15 22:19:05 +01:00
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/// MSP430II - This namespace holds all of the target specific flags that
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/// instruction info tracks.
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///
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namespace MSP430II {
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enum {
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SizeShift = 2,
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SizeMask = 7 << SizeShift,
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SizeUnknown = 0 << SizeShift,
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SizeSpecial = 1 << SizeShift,
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Size2Bytes = 2 << SizeShift,
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Size4Bytes = 3 << SizeShift,
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Size6Bytes = 4 << SizeShift
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};
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2015-06-23 11:49:53 +02:00
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}
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2010-01-15 22:19:05 +01:00
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2011-07-01 19:57:27 +02:00
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class MSP430InstrInfo : public MSP430GenInstrInfo {
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2009-05-03 14:57:15 +02:00
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const MSP430RegisterInfo RI;
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2013-11-19 01:57:56 +01:00
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virtual void anchor();
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2009-05-03 14:57:15 +02:00
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public:
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2014-06-27 03:14:50 +02:00
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explicit MSP430InstrInfo(MSP430Subtarget &STI);
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2009-05-03 14:57:15 +02:00
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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2014-04-29 09:58:09 +02:00
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const TargetRegisterInfo &getRegisterInfo() const { return RI; }
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2009-05-03 15:02:04 +02:00
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2010-07-11 08:53:30 +02:00
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void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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2014-04-29 09:58:09 +02:00
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bool KillSrc) const override;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill,
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int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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2009-05-03 15:11:04 +02:00
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2010-01-15 22:19:05 +01:00
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unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
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2009-10-21 21:17:18 +02:00
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// Branch folding goodness
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2014-04-29 09:58:09 +02:00
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bool
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ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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bool isUnpredicatedTerminator(const MachineInstr *MI) const override;
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2009-10-21 21:17:18 +02:00
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bool AnalyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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2014-04-29 09:58:09 +02:00
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bool AllowModify) const override;
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2009-10-21 21:17:18 +02:00
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2014-04-29 09:58:09 +02:00
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unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
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2009-10-21 21:17:18 +02:00
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unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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2015-06-11 21:30:37 +02:00
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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2014-04-29 09:58:09 +02:00
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DebugLoc DL) const override;
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2009-05-03 15:15:22 +02:00
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2009-05-03 14:57:15 +02:00
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};
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2015-06-23 11:49:53 +02:00
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}
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2009-05-03 14:57:15 +02:00
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#endif
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