2003-11-20 04:32:25 +01:00
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//===-- RegAllocLinearScan.cpp - Linear Scan register allocator -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a linear scan register allocator.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegInfo.h"
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#include "llvm/Support/CFG.h"
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#include "Support/Debug.h"
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#include "Support/DepthFirstIterator.h"
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#include "Support/Statistic.h"
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#include "Support/STLExtras.h"
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#include <iostream>
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using namespace llvm;
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namespace {
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Statistic<> numSpilled ("ra-linearscan", "Number of registers spilled");
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class RA : public MachineFunctionPass {
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public:
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typedef std::vector<const LiveIntervals::Interval*> IntervalPtrs;
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private:
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MachineFunction* mf_;
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const TargetMachine* tm_;
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const MRegisterInfo* mri_;
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MachineBasicBlock* currentMbb_;
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MachineBasicBlock::iterator currentInstr_;
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typedef LiveIntervals::Intervals Intervals;
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const Intervals* li_;
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IntervalPtrs active_, inactive_;
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typedef std::vector<unsigned> Regs;
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Regs tempUseOperands_;
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Regs tempDefOperands_;
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Regs reserved_;
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typedef LiveIntervals::MachineBasicBlockPtrs MachineBasicBlockPtrs;
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MachineBasicBlockPtrs mbbs_;
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typedef std::vector<unsigned> Phys2VirtMap;
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Phys2VirtMap p2vMap_;
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typedef std::map<unsigned, unsigned> Virt2PhysMap;
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Virt2PhysMap v2pMap_;
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typedef std::map<unsigned, int> Virt2StackSlotMap;
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Virt2StackSlotMap v2ssMap_;
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int instrAdded_;
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public:
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virtual const char* getPassName() const {
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return "Linear Scan Register Allocator";
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}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<LiveVariables>();
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AU.addRequired<LiveIntervals>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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private:
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/// runOnMachineFunction - register allocate the whole function
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bool runOnMachineFunction(MachineFunction&);
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/// processActiveIntervals - expire old intervals and move
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/// non-overlapping ones to the incative list
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void processActiveIntervals(Intervals::const_iterator cur);
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/// processInactiveIntervals - expire old intervals and move
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/// overlapping ones to the active list
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void processInactiveIntervals(Intervals::const_iterator cur);
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/// assignStackSlotAtInterval - choose and spill
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/// interval. Currently we spill the interval with the last
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/// end point in the active and inactive lists and the current
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/// interval
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void assignStackSlotAtInterval(Intervals::const_iterator cur);
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///
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/// register handling helpers
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///
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/// reservePhysReg - reserves a physical register and spills
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/// any value assigned to it if any
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void reservePhysReg(unsigned reg);
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/// clearReservedPhysReg - marks pysical register as free for
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/// use
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void clearReservedPhysReg(unsigned reg);
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/// physRegAvailable - returns true if the specifed physical
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/// register is available
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bool physRegAvailable(unsigned physReg);
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/// getFreePhysReg - return a free physical register for this
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/// virtual register if we have one, otherwise return 0
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unsigned getFreePhysReg(unsigned virtReg);
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/// tempPhysRegAvailable - returns true if the specifed
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/// temporary physical register is available
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bool tempPhysRegAvailable(unsigned physReg);
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/// getFreeTempPhysReg - return a free temprorary physical
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/// register for this register class if we have one (should
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/// never return 0)
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unsigned getFreeTempPhysReg(const TargetRegisterClass* rc);
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/// getFreeTempPhysReg - return a free temprorary physical
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/// register for this virtual register if we have one (should
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/// never return 0)
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unsigned getFreeTempPhysReg(unsigned virtReg) {
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const TargetRegisterClass* rc =
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mf_->getSSARegMap()->getRegClass(virtReg);
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return getFreeTempPhysReg(rc);
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}
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/// assignVirt2PhysReg - assigns the free physical register to
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/// the virtual register passed as arguments
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void assignVirt2PhysReg(unsigned virtReg, unsigned physReg);
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/// clearVirtReg - free the physical register associated with this
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/// virtual register and disassociate virtual->physical and
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/// physical->virtual mappings
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void clearVirtReg(unsigned virtReg);
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/// assignVirt2StackSlot - assigns this virtual register to a
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/// stack slot
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void assignVirt2StackSlot(unsigned virtReg);
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2003-12-04 04:57:28 +01:00
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/// getStackSlot - returns the offset of the specified
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/// register on the stack
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int getStackSlot(unsigned virtReg);
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2003-11-20 04:32:25 +01:00
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/// spillVirtReg - spills the virtual register
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void spillVirtReg(unsigned virtReg);
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/// loadPhysReg - loads to the physical register the value of
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/// the virtual register specifed. Virtual register must have
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/// an assigned stack slot
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void loadVirt2PhysReg(unsigned virtReg, unsigned physReg);
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void printVirt2PhysMap() const {
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std::cerr << "allocated registers:\n";
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for (Virt2PhysMap::const_iterator
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i = v2pMap_.begin(), e = v2pMap_.end(); i != e; ++i) {
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std::cerr << '[' << i->first << ','
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<< mri_->getName(i->second) << "]\n";
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}
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std::cerr << '\n';
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}
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void printIntervals(const char* const str,
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RA::IntervalPtrs::const_iterator i,
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RA::IntervalPtrs::const_iterator e) const {
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if (str) std::cerr << str << " intervals:\n";
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for (; i != e; ++i) {
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std::cerr << "\t\t" << **i << " -> ";
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if ((*i)->reg < MRegisterInfo::FirstVirtualRegister) {
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std::cerr << mri_->getName((*i)->reg);
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}
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else {
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std::cerr << mri_->getName(v2pMap_.find((*i)->reg)->second);
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}
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std::cerr << '\n';
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}
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}
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};
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}
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bool RA::runOnMachineFunction(MachineFunction &fn) {
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mf_ = &fn;
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tm_ = &fn.getTarget();
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mri_ = tm_->getRegisterInfo();
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li_ = &getAnalysis<LiveIntervals>().getIntervals();
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active_.clear();
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inactive_.clear();
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mbbs_ = getAnalysis<LiveIntervals>().getOrderedMachineBasicBlockPtrs();
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p2vMap_.resize(MRegisterInfo::FirstVirtualRegister-1);
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p2vMap_.clear();
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v2pMap_.clear();
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v2ssMap_.clear();
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2003-12-01 00:40:39 +01:00
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DEBUG(
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for (MachineBasicBlockPtrs::iterator
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mbbi = mbbs_.begin(), mbbe = mbbs_.end();
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mbbi != mbbe; ++mbbi) {
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MachineBasicBlock* mbb = *mbbi;
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std::cerr << mbb->getBasicBlock()->getName() << '\n';
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for (MachineBasicBlock::iterator
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ii = mbb->begin(), ie = mbb->end();
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ii != ie; ++ii) {
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MachineInstr* instr = *ii;
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std::cerr << "\t";
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instr->print(std::cerr, *tm_);
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}
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}
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);
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2003-11-20 04:32:25 +01:00
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// FIXME: this will work only for the X86 backend. I need to
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// device an algorthm to select the minimal (considering register
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// aliasing) number of temp registers to reserve so that we have 2
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// registers for each register class available.
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// reserve R32: EDI, EBX,
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// R16: DI, BX,
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// R8: DH, BH,
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// RFP: FP5, FP6
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reserved_.push_back(19); /* EDI */
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reserved_.push_back(17); /* EBX */
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reserved_.push_back(12); /* DI */
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reserved_.push_back( 7); /* BX */
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reserved_.push_back(11); /* DH */
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reserved_.push_back( 4); /* BH */
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reserved_.push_back(28); /* FP5 */
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reserved_.push_back(29); /* FP6 */
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// liner scan algorithm
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for (Intervals::const_iterator
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i = li_->begin(), e = li_->end(); i != e; ++i) {
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DEBUG(std::cerr << "processing current interval: " << *i << '\n');
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DEBUG(printIntervals("\tactive", active_.begin(), active_.end()));
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DEBUG(printIntervals("\tinactive", inactive_.begin(), inactive_.end()));
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processActiveIntervals(i);
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// processInactiveIntervals(i);
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// if this register is preallocated, look for an interval that
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// overlaps with it and assign it to a memory location
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if (i->reg < MRegisterInfo::FirstVirtualRegister) {
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reservePhysReg(i->reg);
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active_.push_back(&*i);
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}
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// otherwise we are allocating a virtual register. try to find
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// a free physical register or spill an interval in order to
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// assign it one (we could spill the current though).
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else {
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unsigned physReg = getFreePhysReg(i->reg);
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if (!physReg) {
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assignStackSlotAtInterval(i);
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}
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else {
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assignVirt2PhysReg(i->reg, physReg);
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active_.push_back(&*i);
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}
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}
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}
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DEBUG(std::cerr << "finished register allocation\n");
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DEBUG(printVirt2PhysMap());
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DEBUG(std::cerr << "Rewrite machine code:\n");
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for (MachineBasicBlockPtrs::iterator
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mbbi = mbbs_.begin(), mbbe = mbbs_.end(); mbbi != mbbe; ++mbbi) {
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instrAdded_ = 0;
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currentMbb_ = *mbbi;
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for (currentInstr_ = currentMbb_->begin();
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currentInstr_ != currentMbb_->end(); ++currentInstr_) {
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DEBUG(std::cerr << "\tinstruction: ";
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(*currentInstr_)->print(std::cerr, *tm_););
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// use our current mapping and actually replace and
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// virtual register with its allocated physical registers
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DEBUG(std::cerr << "\t\treplacing virtual registers with mapped "
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"physical registers:\n");
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for (unsigned i = 0, e = (*currentInstr_)->getNumOperands();
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i != e; ++i) {
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MachineOperand& op = (*currentInstr_)->getOperand(i);
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if (op.isVirtualRegister()) {
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unsigned virtReg = op.getAllocatedRegNum();
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unsigned physReg = v2pMap_[virtReg];
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// if this virtual registers lives on the stack,
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// load it to a temporary physical register
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if (physReg) {
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DEBUG(std::cerr << "\t\t\t%reg" << virtReg
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<< " -> " << mri_->getName(physReg) << '\n');
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(*currentInstr_)->SetMachineOperandReg(i, physReg);
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}
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}
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}
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DEBUG(std::cerr << "\t\tloading temporarily used operands to "
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"registers:\n");
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for (unsigned i = 0, e = (*currentInstr_)->getNumOperands();
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i != e; ++i) {
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MachineOperand& op = (*currentInstr_)->getOperand(i);
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if (op.isVirtualRegister() && op.opIsUse()) {
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unsigned virtReg = op.getAllocatedRegNum();
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unsigned physReg = v2pMap_[virtReg];
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if (!physReg) {
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physReg = getFreeTempPhysReg(virtReg);
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}
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loadVirt2PhysReg(virtReg, physReg);
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tempUseOperands_.push_back(virtReg);
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(*currentInstr_)->SetMachineOperandReg(i, physReg);
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}
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}
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DEBUG(std::cerr << "\t\tclearing temporarily used operands:\n");
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for (unsigned i = 0, e = tempUseOperands_.size(); i != e; ++i) {
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clearVirtReg(tempUseOperands_[i]);
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}
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tempUseOperands_.clear();
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DEBUG(std::cerr << "\t\tassigning temporarily defined operands to "
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"registers:\n");
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for (unsigned i = 0, e = (*currentInstr_)->getNumOperands();
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i != e; ++i) {
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MachineOperand& op = (*currentInstr_)->getOperand(i);
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if (op.isVirtualRegister() && !op.opIsUse()) {
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unsigned virtReg = op.getAllocatedRegNum();
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unsigned physReg = v2pMap_[virtReg];
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if (!physReg) {
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physReg = getFreeTempPhysReg(virtReg);
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}
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if (op.opIsDefAndUse()) {
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loadVirt2PhysReg(virtReg, physReg);
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}
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else {
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assignVirt2PhysReg(virtReg, physReg);
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}
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tempDefOperands_.push_back(virtReg);
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(*currentInstr_)->SetMachineOperandReg(i, physReg);
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}
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}
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// if the instruction is a two address instruction and the
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// source operands are not identical we need to insert
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// extra instructions.
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unsigned opcode = (*currentInstr_)->getOpcode();
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if (tm_->getInstrInfo().isTwoAddrInstr(opcode) &&
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(*currentInstr_)->getOperand(0).getAllocatedRegNum() !=
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(*currentInstr_)->getOperand(1).getAllocatedRegNum()) {
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assert((*currentInstr_)->getOperand(1).isRegister() &&
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(*currentInstr_)->getOperand(1).getAllocatedRegNum() &&
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(*currentInstr_)->getOperand(1).opIsUse() &&
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"Two address instruction invalid");
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unsigned regA =
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(*currentInstr_)->getOperand(0).getAllocatedRegNum();
|
|
|
|
unsigned regB =
|
|
|
|
(*currentInstr_)->getOperand(1).getAllocatedRegNum();
|
|
|
|
unsigned regC =
|
|
|
|
((*currentInstr_)->getNumOperands() > 2 &&
|
|
|
|
(*currentInstr_)->getOperand(2).isRegister()) ?
|
|
|
|
(*currentInstr_)->getOperand(2).getAllocatedRegNum() :
|
|
|
|
0;
|
|
|
|
|
|
|
|
const TargetRegisterClass* rc = mri_->getRegClass(regA);
|
|
|
|
|
|
|
|
// special case: "a = b op a". If b is a temporary
|
|
|
|
// reserved register rewrite as: "b = b op a; a = b"
|
|
|
|
// otherwise use a temporary reserved register t and
|
|
|
|
// rewrite as: "t = b; t = t op a; a = t"
|
|
|
|
if (regC && regA == regC) {
|
|
|
|
// b is a temp reserved register
|
|
|
|
if (find(reserved_.begin(), reserved_.end(),
|
|
|
|
regB) != reserved_.end()) {
|
|
|
|
(*currentInstr_)->SetMachineOperandReg(0, regB);
|
|
|
|
++currentInstr_;
|
|
|
|
instrAdded_ += mri_->copyRegToReg(*currentMbb_,
|
|
|
|
currentInstr_,
|
|
|
|
regA,
|
|
|
|
regB,
|
|
|
|
rc);
|
|
|
|
--currentInstr_;
|
|
|
|
}
|
|
|
|
// b is just a normal register
|
|
|
|
else {
|
|
|
|
unsigned tempReg = getFreeTempPhysReg(rc);
|
|
|
|
assert (tempReg &&
|
|
|
|
"no free temp reserved physical register?");
|
|
|
|
instrAdded_ += mri_->copyRegToReg(*currentMbb_,
|
|
|
|
currentInstr_,
|
|
|
|
tempReg,
|
|
|
|
regB,
|
|
|
|
rc);
|
|
|
|
(*currentInstr_)->SetMachineOperandReg(0, tempReg);
|
|
|
|
(*currentInstr_)->SetMachineOperandReg(1, tempReg);
|
|
|
|
++currentInstr_;
|
|
|
|
instrAdded_ += mri_->copyRegToReg(*currentMbb_,
|
|
|
|
currentInstr_,
|
|
|
|
regA,
|
|
|
|
tempReg,
|
|
|
|
rc);
|
|
|
|
--currentInstr_;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
// "a = b op c" gets rewritten to "a = b; a = a op c"
|
|
|
|
else {
|
|
|
|
instrAdded_ += mri_->copyRegToReg(*currentMbb_,
|
|
|
|
currentInstr_,
|
|
|
|
regA,
|
|
|
|
regB,
|
|
|
|
rc);
|
|
|
|
(*currentInstr_)->SetMachineOperandReg(1, regA);
|
|
|
|
}
|
|
|
|
}
|
2003-12-01 00:40:39 +01:00
|
|
|
|
|
|
|
DEBUG(std::cerr << "\t\tspilling temporarily defined operands "
|
|
|
|
"of this instruction:\n");
|
|
|
|
++currentInstr_; // we want to insert after this instruction
|
|
|
|
for (unsigned i = 0, e = tempDefOperands_.size(); i != e; ++i) {
|
|
|
|
spillVirtReg(tempDefOperands_[i]);
|
|
|
|
}
|
|
|
|
--currentInstr_; // restore currentInstr_ iterator
|
|
|
|
tempDefOperands_.clear();
|
2003-11-20 04:32:25 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
for (unsigned i = 0, e = p2vMap_.size(); i != e; ++i) {
|
|
|
|
assert(p2vMap_[i] != i &&
|
|
|
|
"reserved physical registers at end of basic block?");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
void RA::processActiveIntervals(Intervals::const_iterator cur)
|
|
|
|
{
|
|
|
|
DEBUG(std::cerr << "\tprocessing active intervals:\n");
|
|
|
|
for (IntervalPtrs::iterator i = active_.begin(); i != active_.end();) {
|
|
|
|
unsigned reg = (*i)->reg;
|
|
|
|
// remove expired intervals. we expire earlier because this if
|
|
|
|
// an interval expires this is going to be the last use. in
|
|
|
|
// this case we can reuse the register for a def in the same
|
|
|
|
// instruction
|
|
|
|
if ((*i)->expired(cur->start() + 1)) {
|
|
|
|
DEBUG(std::cerr << "\t\tinterval " << **i << " expired\n");
|
|
|
|
if (reg < MRegisterInfo::FirstVirtualRegister) {
|
|
|
|
clearReservedPhysReg(reg);
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
p2vMap_[v2pMap_[reg]] = 0;
|
|
|
|
}
|
|
|
|
// remove interval from active
|
|
|
|
i = active_.erase(i);
|
|
|
|
}
|
|
|
|
// move not active intervals to inactive list
|
|
|
|
// else if (!(*i)->overlaps(curIndex)) {
|
|
|
|
// DEBUG(std::cerr << "\t\t\tinterval " << **i << " inactive\n");
|
|
|
|
// unmarkReg(virtReg);
|
|
|
|
// // add interval to inactive
|
|
|
|
// inactive_.push_back(*i);
|
|
|
|
// // remove interval from active
|
|
|
|
// i = active_.erase(i);
|
|
|
|
// }
|
|
|
|
else {
|
|
|
|
++i;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void RA::processInactiveIntervals(Intervals::const_iterator cur)
|
|
|
|
{
|
|
|
|
// DEBUG(std::cerr << "\tprocessing inactive intervals:\n");
|
|
|
|
// for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end();) {
|
|
|
|
// unsigned virtReg = (*i)->reg;
|
|
|
|
// // remove expired intervals
|
|
|
|
// if ((*i)->expired(curIndex)) {
|
|
|
|
// DEBUG(std::cerr << "\t\t\tinterval " << **i << " expired\n");
|
|
|
|
// freePhysReg(virtReg);
|
|
|
|
// // remove from inactive
|
|
|
|
// i = inactive_.erase(i);
|
|
|
|
// }
|
|
|
|
// // move re-activated intervals in active list
|
|
|
|
// else if ((*i)->overlaps(curIndex)) {
|
|
|
|
// DEBUG(std::cerr << "\t\t\tinterval " << **i << " active\n");
|
|
|
|
// markReg(virtReg);
|
|
|
|
// // add to active
|
|
|
|
// active_.push_back(*i);
|
|
|
|
// // remove from inactive
|
|
|
|
// i = inactive_.erase(i);
|
|
|
|
// }
|
|
|
|
// else {
|
|
|
|
// ++i;
|
|
|
|
// }
|
|
|
|
// }
|
|
|
|
}
|
|
|
|
|
|
|
|
void RA::assignStackSlotAtInterval(Intervals::const_iterator cur)
|
|
|
|
{
|
|
|
|
DEBUG(std::cerr << "\t\tassigning stack slot at interval "
|
|
|
|
<< *cur << ":\n");
|
|
|
|
assert(!active_.empty() &&
|
|
|
|
"active set cannot be empty when choosing a register to spill");
|
|
|
|
const TargetRegisterClass* rcCur =
|
|
|
|
mf_->getSSARegMap()->getRegClass(cur->reg);
|
|
|
|
|
|
|
|
// find the interval for a virtual register that ends last in
|
|
|
|
// active and belongs to the same register class as the current
|
|
|
|
// interval
|
|
|
|
IntervalPtrs::iterator lastEndActive = active_.begin();
|
|
|
|
for (IntervalPtrs::iterator e = active_.end();
|
|
|
|
lastEndActive != e; ++lastEndActive) {
|
|
|
|
if ((*lastEndActive)->reg >= MRegisterInfo::FirstVirtualRegister) {
|
|
|
|
const TargetRegisterClass* rc =
|
|
|
|
mri_->getRegClass(v2pMap_[(*lastEndActive)->reg]);
|
|
|
|
if (rcCur == rc) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
for (IntervalPtrs::iterator i = lastEndActive, e = active_.end();
|
|
|
|
i != e; ++i) {
|
|
|
|
if ((*i)->reg >= MRegisterInfo::FirstVirtualRegister) {
|
|
|
|
const TargetRegisterClass* rc =
|
|
|
|
mri_->getRegClass(v2pMap_[(*i)->reg]);
|
|
|
|
if (rcCur == rc &&
|
|
|
|
(*lastEndActive)->end() < (*i)->end()) {
|
|
|
|
lastEndActive = i;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// find the interval for a virtual register that ends last in
|
|
|
|
// inactive and belongs to the same register class as the current
|
|
|
|
// interval
|
|
|
|
IntervalPtrs::iterator lastEndInactive = inactive_.begin();
|
|
|
|
for (IntervalPtrs::iterator e = inactive_.end();
|
|
|
|
lastEndInactive != e; ++lastEndInactive) {
|
|
|
|
if ((*lastEndInactive)->reg >= MRegisterInfo::FirstVirtualRegister) {
|
|
|
|
const TargetRegisterClass* rc =
|
|
|
|
mri_->getRegClass(v2pMap_[(*lastEndInactive)->reg]);
|
|
|
|
if (rcCur == rc) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
for (IntervalPtrs::iterator i = lastEndInactive, e = inactive_.end();
|
|
|
|
i != e; ++i) {
|
|
|
|
if ((*i)->reg >= MRegisterInfo::FirstVirtualRegister) {
|
|
|
|
const TargetRegisterClass* rc =
|
|
|
|
mri_->getRegClass(v2pMap_[(*i)->reg]);
|
|
|
|
if (rcCur == rc &&
|
|
|
|
(*lastEndInactive)->end() < (*i)->end()) {
|
|
|
|
lastEndInactive = i;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned lastEndActiveInactive = 0;
|
|
|
|
if (lastEndActive != active_.end() &&
|
|
|
|
lastEndActiveInactive < (*lastEndActive)->end()) {
|
|
|
|
lastEndActiveInactive = (*lastEndActive)->end();
|
|
|
|
}
|
|
|
|
if (lastEndInactive != inactive_.end() &&
|
|
|
|
lastEndActiveInactive < (*lastEndInactive)->end()) {
|
|
|
|
lastEndActiveInactive = (*lastEndInactive)->end();
|
|
|
|
}
|
|
|
|
|
|
|
|
if (lastEndActiveInactive > cur->end()) {
|
|
|
|
if (lastEndInactive == inactive_.end() ||
|
|
|
|
(*lastEndActive)->end() > (*lastEndInactive)->end()) {
|
|
|
|
assignVirt2StackSlot((*lastEndActive)->reg);
|
|
|
|
active_.erase(lastEndActive);
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
assignVirt2StackSlot((*lastEndInactive)->reg);
|
|
|
|
inactive_.erase(lastEndInactive);
|
|
|
|
}
|
|
|
|
unsigned physReg = getFreePhysReg(cur->reg);
|
|
|
|
assert(physReg && "no free physical register after spill?");
|
|
|
|
assignVirt2PhysReg(cur->reg, physReg);
|
|
|
|
active_.push_back(&*cur);
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
assignVirt2StackSlot(cur->reg);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void RA::reservePhysReg(unsigned physReg)
|
|
|
|
{
|
2003-12-05 12:17:55 +01:00
|
|
|
DEBUG(std::cerr << "\t\t\treserving physical register: "
|
2003-11-20 04:32:25 +01:00
|
|
|
<< mri_->getName(physReg) << '\n');
|
|
|
|
// if this register holds a value spill it
|
|
|
|
unsigned virtReg = p2vMap_[physReg];
|
|
|
|
if (virtReg != 0) {
|
|
|
|
assert(virtReg != physReg && "reserving an already reserved phus reg?");
|
|
|
|
// remove interval from active
|
|
|
|
for (IntervalPtrs::iterator i = active_.begin(), e = active_.end();
|
|
|
|
i != e; ++i) {
|
|
|
|
if ((*i)->reg == virtReg) {
|
|
|
|
active_.erase(i);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2003-12-05 12:17:55 +01:00
|
|
|
assignVirt2StackSlot(virtReg);
|
2003-11-20 04:32:25 +01:00
|
|
|
}
|
|
|
|
p2vMap_[physReg] = physReg; // this denotes a reserved physical register
|
|
|
|
}
|
|
|
|
|
|
|
|
void RA::clearReservedPhysReg(unsigned physReg)
|
|
|
|
{
|
2003-12-05 12:17:55 +01:00
|
|
|
DEBUG(std::cerr << "\t\t\tclearing reserved physical register: "
|
2003-11-20 04:32:25 +01:00
|
|
|
<< mri_->getName(physReg) << '\n');
|
|
|
|
assert(p2vMap_[physReg] == physReg &&
|
|
|
|
"attempt to clear a non reserved physical register");
|
|
|
|
p2vMap_[physReg] = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool RA::physRegAvailable(unsigned physReg)
|
|
|
|
{
|
|
|
|
if (p2vMap_[physReg]) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// if it aliases other registers it is still not free
|
|
|
|
for (const unsigned* as = mri_->getAliasSet(physReg); *as; ++as) {
|
|
|
|
if (p2vMap_[*as]) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// if it is one of the reserved registers it is still not free
|
|
|
|
if (find(reserved_.begin(), reserved_.end(), physReg) != reserved_.end()) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned RA::getFreePhysReg(unsigned virtReg)
|
|
|
|
{
|
|
|
|
DEBUG(std::cerr << "\t\tgetting free physical register: ");
|
|
|
|
const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(virtReg);
|
|
|
|
TargetRegisterClass::iterator reg = rc->allocation_order_begin(*mf_);
|
|
|
|
TargetRegisterClass::iterator regEnd = rc->allocation_order_end(*mf_);
|
|
|
|
|
|
|
|
for (; reg != regEnd; ++reg) {
|
|
|
|
if (physRegAvailable(*reg)) {
|
|
|
|
assert(*reg != 0 && "Cannot use register!");
|
|
|
|
DEBUG(std::cerr << mri_->getName(*reg) << '\n');
|
|
|
|
return *reg; // Found an unused register!
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
DEBUG(std::cerr << "no free register\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool RA::tempPhysRegAvailable(unsigned physReg)
|
|
|
|
{
|
|
|
|
assert(find(reserved_.begin(), reserved_.end(), physReg) != reserved_.end()
|
|
|
|
&& "cannot call this method with a non reserved temp register");
|
|
|
|
|
|
|
|
if (p2vMap_[physReg]) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// if it aliases other registers it is still not free
|
|
|
|
for (const unsigned* as = mri_->getAliasSet(physReg); *as; ++as) {
|
|
|
|
if (p2vMap_[*as]) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned RA::getFreeTempPhysReg(const TargetRegisterClass* rc)
|
|
|
|
{
|
|
|
|
DEBUG(std::cerr << "\t\tgetting free temporary physical register: ");
|
|
|
|
|
|
|
|
for (Regs::const_iterator
|
|
|
|
reg = reserved_.begin(), regEnd = reserved_.end();
|
|
|
|
reg != regEnd; ++reg) {
|
|
|
|
if (rc == mri_->getRegClass(*reg) && tempPhysRegAvailable(*reg)) {
|
|
|
|
assert(*reg != 0 && "Cannot use register!");
|
|
|
|
DEBUG(std::cerr << mri_->getName(*reg) << '\n');
|
|
|
|
return *reg; // Found an unused register!
|
|
|
|
}
|
|
|
|
}
|
|
|
|
assert(0 && "no free temporary physical register?");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void RA::assignVirt2PhysReg(unsigned virtReg, unsigned physReg)
|
|
|
|
{
|
|
|
|
assert((physRegAvailable(physReg) ||
|
|
|
|
find(reserved_.begin(),
|
|
|
|
reserved_.end(),
|
|
|
|
physReg) != reserved_.end()) &&
|
|
|
|
"attempt to allocate to a not available physical register");
|
|
|
|
v2pMap_[virtReg] = physReg;
|
|
|
|
p2vMap_[physReg] = virtReg;
|
|
|
|
}
|
|
|
|
|
|
|
|
void RA::clearVirtReg(unsigned virtReg)
|
|
|
|
{
|
|
|
|
Virt2PhysMap::iterator it = v2pMap_.find(virtReg);
|
|
|
|
assert(it != v2pMap_.end() &&
|
|
|
|
"attempting to clear a not allocated virtual register");
|
|
|
|
unsigned physReg = it->second;
|
|
|
|
p2vMap_[physReg] = 0;
|
|
|
|
v2pMap_[virtReg] = 0; // this marks that this virtual register
|
|
|
|
// lives on the stack
|
|
|
|
DEBUG(std::cerr << "\t\t\tcleared register " << mri_->getName(physReg)
|
|
|
|
<< "\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
void RA::assignVirt2StackSlot(unsigned virtReg)
|
|
|
|
{
|
|
|
|
const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(virtReg);
|
|
|
|
int frameIndex = mf_->getFrameInfo()->CreateStackObject(rc);
|
|
|
|
|
|
|
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bool inserted = v2ssMap_.insert(std::make_pair(virtReg, frameIndex)).second;
|
|
|
|
assert(inserted &&
|
|
|
|
"attempt to assign stack slot to already assigned register?");
|
|
|
|
// if the virtual register was previously assigned clear the mapping
|
|
|
|
// and free the virtual register
|
|
|
|
if (v2pMap_.find(virtReg) != v2pMap_.end()) {
|
|
|
|
clearVirtReg(virtReg);
|
|
|
|
}
|
2003-12-04 04:57:28 +01:00
|
|
|
else {
|
|
|
|
v2pMap_[virtReg] = 0; // this marks that this virtual register
|
|
|
|
// lives on the stack
|
|
|
|
}
|
2003-11-20 04:32:25 +01:00
|
|
|
}
|
|
|
|
|
2003-12-04 04:57:28 +01:00
|
|
|
int RA::getStackSlot(unsigned virtReg)
|
2003-11-20 04:32:25 +01:00
|
|
|
{
|
|
|
|
// use lower_bound so that we can do a possibly O(1) insert later
|
|
|
|
// if necessary
|
2003-12-04 04:57:28 +01:00
|
|
|
Virt2StackSlotMap::iterator it = v2ssMap_.find(virtReg);
|
|
|
|
assert(it != v2ssMap_.end() &&
|
|
|
|
"attempt to get stack slot on register that does not live on the stack");
|
|
|
|
return it->second;
|
2003-11-20 04:32:25 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void RA::spillVirtReg(unsigned virtReg)
|
|
|
|
{
|
|
|
|
DEBUG(std::cerr << "\t\t\tspilling register: " << virtReg);
|
|
|
|
const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(virtReg);
|
2003-12-04 04:57:28 +01:00
|
|
|
int frameIndex = getStackSlot(virtReg);
|
2003-11-20 04:32:25 +01:00
|
|
|
DEBUG(std::cerr << " to stack slot #" << frameIndex << '\n');
|
|
|
|
++numSpilled;
|
|
|
|
instrAdded_ += mri_->storeRegToStackSlot(*currentMbb_, currentInstr_,
|
|
|
|
v2pMap_[virtReg], frameIndex, rc);
|
|
|
|
clearVirtReg(virtReg);
|
|
|
|
}
|
|
|
|
|
|
|
|
void RA::loadVirt2PhysReg(unsigned virtReg, unsigned physReg)
|
|
|
|
{
|
|
|
|
DEBUG(std::cerr << "\t\t\tloading register: " << virtReg);
|
|
|
|
const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(virtReg);
|
2003-12-04 04:57:28 +01:00
|
|
|
int frameIndex = getStackSlot(virtReg);
|
2003-11-20 04:32:25 +01:00
|
|
|
DEBUG(std::cerr << " from stack slot #" << frameIndex << '\n');
|
|
|
|
instrAdded_ += mri_->loadRegFromStackSlot(*currentMbb_, currentInstr_,
|
|
|
|
physReg, frameIndex, rc);
|
|
|
|
assignVirt2PhysReg(virtReg, physReg);
|
|
|
|
}
|
|
|
|
|
|
|
|
FunctionPass* llvm::createLinearScanRegisterAllocator() {
|
|
|
|
return new RA();
|
|
|
|
}
|