llvm-mirror/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt

# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 |& grep {invalid instruction encoding}
# XFAIL: *

# Opcode=1225 Name=VQADDsv16i8 Format=ARM_FORMAT_N3Reg(37)
#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 1| 0: 0: 1: 0| 0: 1: 0: 0| 0: 0: 0: 0| 1: 1: 1: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 0: 1: 1|
# -------------------------------------------------------------------------------------------------
#
# Qm -> bit[0] == 0, otherwise UNDEFINED
0xdb 0xe0 0x40 0xf2
Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. llvm-svn: 139250 2011-09-07 21:42:28 +02:00			`# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 \|& grep {invalid instruction encoding}`
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144 2011-08-09 22:55:18 +02:00			`# XFAIL: *`
A7.3 register encoding Qd -> bit[12] == 0 Qn -> bit[16] == 0 Qm -> bit[0] == 0 If one of these bits is 1, the instruction is UNDEFINED. rdar://problem/9238399 rdar://problem/9238445 llvm-svn: 128949 2011-04-06 00:57:07 +02:00
			`# Opcode=1225 Name=VQADDsv16i8 Format=ARM_FORMAT_N3Reg(37)`
			`# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0`
			`# -------------------------------------------------------------------------------------------------`
			`# \| 1: 1: 1: 1\| 0: 0: 1: 0\| 0: 1: 0: 0\| 0: 0: 0: 0\| 1: 1: 1: 0\| 0: 0: 0: 0\| 1: 1: 0: 1\| 1: 0: 1: 1\|`
			`# -------------------------------------------------------------------------------------------------`
			`#`
			`# Qm -> bit[0] == 0, otherwise UNDEFINED`
			`0xdb 0xe0 0x40 0xf2`