llvm-mirror/test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll

; RUN: llc -verify-machineinstrs < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"

; Function Attrs: nounwind
define <2 x i32> @test1(<4 x i32> %wide.vec) #0 {
entry:
  %strided.vec = shufflevector <4 x i32> %wide.vec, <4 x i32> undef, <2 x i32> <i32 0, i32 2>
  ret <2 x i32> %strided.vec

; CHECK-LABEL: @test1
; CHECK: xxswapd 35, 34
; CHECK: vmrghw 2, 2, 3
; CHECK: blr
}

; Function Attrs: nounwind
define <16 x i8> @test2(<16 x i8> %wide.vec) #0 {
entry:
  %strided.vec = shufflevector <16 x i8> %wide.vec, <16 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 8, i32 9, i32 10, i32 11>
  ret <16 x i8> %strided.vec

; CHECK-LABEL: @test2
; CHECK: vsldoi 2, 2, 2, 12
; CHECK: blr
}

attributes #0 = { nounwind "target-cpu"="pwr7" }
Adding -verify-machineinstrs option to PowerPC tests Currently we have a number of tests that fail with -verify-machineinstrs. To detect this cases earlier we add the option to the testcases with the exception of tests that will currently fail with this option. PR 27456 keeps track of this failures. No code review, as discussed with Hal Finkel. llvm-svn: 277624 2016-08-03 20:17:35 +02:00			`; RUN: llc -verify-machineinstrs < %s \| FileCheck %s`
[PowerPC] Don't always consider P8Altivec-only masks in LowerVECTOR_SHUFFLE LowerVECTOR_SHUFFLE needs to decide whether to pass a vector shuffle off to the TableGen-generated matching code, and it does this by testing the same predicates used by the TableGen files. Unfortunately, when we added new P8Altivec-only predicates, we started universally testing them in LowerVECTOR_SHUFFLE, and if then matched when targeting a system prior to a P8, we'd end up with a selection failure. llvm-svn: 246675 2015-09-02 18:52:37 +02:00			`target datalayout = "E-m:e-i64:64-n32:64"`
			`target triple = "powerpc64-unknown-linux-gnu"`

			`; Function Attrs: nounwind`
			`define <2 x i32> @test1(<4 x i32> %wide.vec) #0 {`
			`entry:`
			`%strided.vec = shufflevector <4 x i32> %wide.vec, <4 x i32> undef, <2 x i32> <i32 0, i32 2>`
			`ret <2 x i32> %strided.vec`

			`; CHECK-LABEL: @test1`
[PowerPC] Cannonicalize applicable vector shift immediates as swaps This patch corresponds to review: http://reviews.llvm.org/D21358 Vector shifts that have the same semantics as a vector swap are cannonicalized as such to provide additional opportunities for swap removal optimization to remove unnecessary swaps. llvm-svn: 275168 2016-07-12 14:16:27 +02:00			`; CHECK: xxswapd 35, 34`
			`; CHECK: vmrghw 2, 2, 3`
[PowerPC] Don't always consider P8Altivec-only masks in LowerVECTOR_SHUFFLE LowerVECTOR_SHUFFLE needs to decide whether to pass a vector shuffle off to the TableGen-generated matching code, and it does this by testing the same predicates used by the TableGen files. Unfortunately, when we added new P8Altivec-only predicates, we started universally testing them in LowerVECTOR_SHUFFLE, and if then matched when targeting a system prior to a P8, we'd end up with a selection failure. llvm-svn: 246675 2015-09-02 18:52:37 +02:00			`; CHECK: blr`
			`}`

			`; Function Attrs: nounwind`
			`define <16 x i8> @test2(<16 x i8> %wide.vec) #0 {`
			`entry:`
			`%strided.vec = shufflevector <16 x i8> %wide.vec, <16 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 8, i32 9, i32 10, i32 11>`
			`ret <16 x i8> %strided.vec`

			`; CHECK-LABEL: @test2`
			`; CHECK: vsldoi 2, 2, 2, 12`
			`; CHECK: blr`
			`}`

			`attributes #0 = { nounwind "target-cpu"="pwr7" }`