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llvm-mirror/test/CodeGen/PowerPC/remove-redundant-load-imm.ll

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[PowerPC] Remove redundant load immediate instructions Currently PowerPC backend emits code like this: r3 = li 0 std r3, 264(r1) r3 = li 0 std r3, 272(r1) This patch fixes that and other cases where a register already contains a value that is loaded so we will get: r3 = li 0 std r3, 264(r1) std r3, 272(r1) Differential Revision: https://reviews.llvm.org/D64220 llvm-svn: 366840
2019-07-23 21:11:07 +02:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr9 -O3 < %s | FileCheck %s -check-prefix=PPC64LE
target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu"
@global.6 = external global i32*
declare void @barney.88(i1, i32*)
declare void @barney.94(i8*, i32)
[PowerPC][NFC] Avoid checking non-relevant .cfi instructions Summary: This is brought up in https://reviews.llvm.org/D64662?id=209923#inline-599490 CFI information are non-relevant to quite some testcases, we should get rid of checking them when its unecessary. This patch avoid generating cfi info in testcases that are not testing prolog/epilog or exception handling. Reviewers: kbarton, hfinkel, nemanjai, #powerpc Reviewed By: hfinkel Subscribers: MaskRay, shchenz, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67016 llvm-svn: 370505
2019-08-30 21:24:25 +02:00
define void @redundancy_on_ppc_only(i1 %arg7) nounwind {
[PowerPC] Remove redundant load immediate instructions Currently PowerPC backend emits code like this: r3 = li 0 std r3, 264(r1) r3 = li 0 std r3, 272(r1) This patch fixes that and other cases where a register already contains a value that is loaded so we will get: r3 = li 0 std r3, 264(r1) std r3, 272(r1) Differential Revision: https://reviews.llvm.org/D64220 llvm-svn: 366840
2019-07-23 21:11:07 +02:00
; PPC64LE-LABEL: redundancy_on_ppc_only:
; PPC64LE: # %bb.0: # %bb
; PPC64LE-NEXT: mflr 0
; PPC64LE-NEXT: andi. 3, 3, 1
; PPC64LE-NEXT: std 0, 16(1)
; PPC64LE-NEXT: stdu 1, -32(1)
; PPC64LE-NEXT: li 3, 1
; PPC64LE-NEXT: li 4, 0
[PowerPC] Add some InstAlias definitions Summary: This patch add the InstAlias definitions for below instructions. ADDI ADDIS ADDI8 ADDIS8 RLWINM8 ISEL ISEL8 OR OR_rec ORI ORI8 XORI8 CNTLZW8 CNTLZW8_rec TEND TSR RFEBB NOR NOR_rec MTCRF SUBF SUBF_rec SUBFC SUBFC_rec RLDICL_32_64 TW Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77559
2020-05-24 16:05:28 +02:00
; PPC64LE-NEXT: iselgt 3, 3, 4
[PowerPC] Remove redundant load immediate instructions Currently PowerPC backend emits code like this: r3 = li 0 std r3, 264(r1) r3 = li 0 std r3, 272(r1) This patch fixes that and other cases where a register already contains a value that is loaded so we will get: r3 = li 0 std r3, 264(r1) std r3, 272(r1) Differential Revision: https://reviews.llvm.org/D64220 llvm-svn: 366840
2019-07-23 21:11:07 +02:00
; PPC64LE-NEXT: bl barney.88
; PPC64LE-NEXT: nop
; PPC64LE-NEXT: addi 1, 1, 32
; PPC64LE-NEXT: ld 0, 16(1)
; PPC64LE-NEXT: mtlr 0
; PPC64LE-NEXT: blr
bb:
br label %bb10
bb10: ; preds = %bb
call void @barney.88(i1 %arg7, i32* null)
ret void
}
[PowerPC][NFC] Avoid checking non-relevant .cfi instructions Summary: This is brought up in https://reviews.llvm.org/D64662?id=209923#inline-599490 CFI information are non-relevant to quite some testcases, we should get rid of checking them when its unecessary. This patch avoid generating cfi info in testcases that are not testing prolog/epilog or exception handling. Reviewers: kbarton, hfinkel, nemanjai, #powerpc Reviewed By: hfinkel Subscribers: MaskRay, shchenz, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67016 llvm-svn: 370505
2019-08-30 21:24:25 +02:00
define void @redundancy_on_ppc_and_other_targets() nounwind {
[PowerPC] Remove redundant load immediate instructions Currently PowerPC backend emits code like this: r3 = li 0 std r3, 264(r1) r3 = li 0 std r3, 272(r1) This patch fixes that and other cases where a register already contains a value that is loaded so we will get: r3 = li 0 std r3, 264(r1) std r3, 272(r1) Differential Revision: https://reviews.llvm.org/D64220 llvm-svn: 366840
2019-07-23 21:11:07 +02:00
; PPC64LE-LABEL: redundancy_on_ppc_and_other_targets:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: mflr 0
; PPC64LE-NEXT: std 0, 16(1)
; PPC64LE-NEXT: stdu 1, -32(1)
; PPC64LE-NEXT: addis 3, 2, .LC0@toc@ha
; PPC64LE-NEXT: li 4, 0
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics tryLatency compares two sched candidates. For the top zone it prefers the one with lesser depth, but only if that depth is greater than the total latency of the instructions we've already scheduled -- otherwise its latency would be hidden and there would be no stall. Unfortunately it only tests the depth of one of the candidates. This can lead to situations where the TopDepthReduce heuristic does not kick in, but a lower priority heuristic chooses the other candidate, whose depth *is* greater than the already scheduled latency, which causes a stall. The fix is to apply the heuristic if the depth of *either* candidate is greater than the already scheduled latency. All this also applies to the BotHeightReduce heuristic in the bottom zone. Differential Revision: https://reviews.llvm.org/D72392
2020-01-07 16:43:46 +01:00
; PPC64LE-NEXT: ld 3, .LC0@toc@l(3)
[PowerPC] Remove redundant load immediate instructions Currently PowerPC backend emits code like this: r3 = li 0 std r3, 264(r1) r3 = li 0 std r3, 272(r1) This patch fixes that and other cases where a register already contains a value that is loaded so we will get: r3 = li 0 std r3, 264(r1) std r3, 272(r1) Differential Revision: https://reviews.llvm.org/D64220 llvm-svn: 366840
2019-07-23 21:11:07 +02:00
; PPC64LE-NEXT: std 4, 0(3)
; PPC64LE-NEXT: bl barney.94
; PPC64LE-NEXT: nop
store i32* null, i32** @global.6
call void @barney.94(i8* undef, i32 0)
unreachable
}
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