llvm-mirror/test/CodeGen/ARM/2012-08-08-legalize-unaligned.ll

; RUN: llc < %s
; PR13111

target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32"
target triple = "armv7-none-linux-gnueabi"

define void @test_hi_char8() noinline {
entry:
  %0 = load <4 x i8>, <4 x i8>* undef, align 1
  store <4 x i8> %0, <4 x i8>* null, align 4
  ret void
}
Fix the legalization of ExtLoad on ARM. ExpandUnalignedLoad did not properly handle the cases where the memory value type was illegal. PR 13111. llvm-svn: 161565 2012-08-09 03:56:44 +02:00			`; RUN: llc < %s`
			`; PR13111`

			`target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32"`
			`target triple = "armv7-none-linux-gnueabi"`

			`define void @test_hi_char8() noinline {`
			`entry:`
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=\|:\|^)\sload (?:atomic )?(?:volatile )?(.?))(\| addrspace\(\d+\) )\($\| (?:%\|@\|null\|undef\|blockaddress\|getelementptr\|addrspacecast\|bitcast\|inttoptr\|\[\[[a-zA-Z]\|\{\{).$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794 2015-02-27 22:17:42 +01:00			`%0 = load <4 x i8>, <4 x i8>* undef, align 1`
Fix the legalization of ExtLoad on ARM. ExpandUnalignedLoad did not properly handle the cases where the memory value type was illegal. PR 13111. llvm-svn: 161565 2012-08-09 03:56:44 +02:00			`store <4 x i8> %0, <4 x i8>* null, align 4`
			`ret void`
			`}`