llvm-mirror/lib/Target/Hexagon/HexagonInstrInfoV5.td

//=- HexagonInstrInfoV5.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes the Hexagon V5 instructions in TableGen format.
//
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
// XTYPE/MPY
//===----------------------------------------------------------------------===//

let isCodeGenOnly = 0 in
def S2_asr_i_p_rnd : S_2OpInstImm<"asr", 0b110, 0b111, u6Imm,
      [(set I64:$dst,
            (sra (i64 (add (i64 (sra I64:$src1, u6ImmPred:$src2)), 1)),
                 (i32 1)))], 1>,
      Requires<[HasV5T]> {
  bits<6> src2;
  let Inst{13-8} = src2;
}

let isCodeGenOnly = 0 in
def C4_fastcorner9 : T_LOGICAL_2OP<"fastcorner9", 0b000, 0, 0>,
  Requires<[HasV5T]> {
  let Inst{13,7,4} = 0b111;
}

let isCodeGenOnly = 0 in
def C4_fastcorner9_not : T_LOGICAL_2OP<"!fastcorner9", 0b000, 0, 0>,
  Requires<[HasV5T]> {
  let Inst{20,13,7,4} = 0b1111;
}

def SDTHexagonFCONST32 : SDTypeProfile<1, 1, [
                                            SDTCisVT<0, f32>,
                                            SDTCisPtrTy<1>]>;
def HexagonFCONST32 : SDNode<"HexagonISD::FCONST32",     SDTHexagonFCONST32>;

let isReMaterializable = 1, isMoveImm = 1 in
def FCONST32_nsdata : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
              "$dst = CONST32(#$global)",
              [(set (f32 IntRegs:$dst),
              (HexagonFCONST32 tglobaladdr:$global))]>,
               Requires<[HasV5T]>;

let isReMaterializable = 1, isMoveImm = 1 in
def CONST64_Float_Real : LDInst<(outs DoubleRegs:$dst), (ins f64imm:$src1),
                       "$dst = CONST64(#$src1)",
                       [(set DoubleRegs:$dst, fpimm:$src1)]>,
          Requires<[HasV5T]>;

let isReMaterializable = 1, isMoveImm = 1 in
def CONST32_Float_Real : LDInst<(outs IntRegs:$dst), (ins f32imm:$src1),
                       "$dst = CONST32(#$src1)",
                       [(set IntRegs:$dst, fpimm:$src1)]>,
          Requires<[HasV5T]>;

// Transfer immediate float.
// Only works with single precision fp value.
// For double precision, use CONST64_float_real, as 64bit transfer
// can only hold 40-bit values - 32 from const ext + 8 bit immediate.
// Make sure that complexity is more than the CONST32 pattern in
// HexagonInstrInfo.td patterns.
let isExtended = 1, opExtendable = 1, isMoveImm = 1, isReMaterializable = 1,
isPredicable = 1, AddedComplexity = 30, validSubTargets = HasV5SubT,
isCodeGenOnly = 1 in
def TFRI_f : ALU32_ri<(outs IntRegs:$dst), (ins f32Ext:$src1),
           "$dst = #$src1",
           [(set IntRegs:$dst, fpimm:$src1)]>,
          Requires<[HasV5T]>;

let isExtended = 1, opExtendable = 2, isPredicated = 1,
hasSideEffects = 0, validSubTargets = HasV5SubT in
def TFRI_cPt_f : ALU32_ri<(outs IntRegs:$dst),
                          (ins PredRegs:$src1, f32Ext:$src2),
           "if ($src1) $dst = #$src2",
           []>,
          Requires<[HasV5T]>;

let isExtended = 1, opExtendable = 2, isPredicated = 1, isPredicatedFalse = 1,
hasSideEffects = 0, validSubTargets = HasV5SubT in
def TFRI_cNotPt_f : ALU32_ri<(outs IntRegs:$dst),
                             (ins PredRegs:$src1, f32Ext:$src2),
           "if (!$src1) $dst =#$src2",
           []>,
          Requires<[HasV5T]>;

def SDTHexagonI32I64: SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
                                           SDTCisVT<1, i64>]>;

def HexagonPOPCOUNT: SDNode<"HexagonISD::POPCOUNT", SDTHexagonI32I64>;

let hasNewValue = 1, validSubTargets = HasV5SubT, isCodeGenOnly = 0 in
def S5_popcountp : ALU64_rr<(outs IntRegs:$Rd), (ins DoubleRegs:$Rss),
  "$Rd = popcount($Rss)",
  [(set I32:$Rd, (HexagonPOPCOUNT I64:$Rss))], "", S_2op_tc_2_SLOT23>,
  Requires<[HasV5T]> {
    bits<5> Rd;
    bits<5> Rss;

    let IClass = 0b1000;

    let Inst{27-21} = 0b1000011;
    let Inst{7-5} = 0b011;
    let Inst{4-0} = Rd;
    let Inst{20-16} = Rss;
  }

defm: Loadx_pat<load, f32, s11_2ExtPred, L2_loadri_io>;
defm: Loadx_pat<load, f64, s11_3ExtPred, L2_loadrd_io>;

defm: Storex_pat<store, F32, s11_2ExtPred, S2_storeri_io>;
defm: Storex_pat<store, F64, s11_3ExtPred, S2_storerd_io>;

let isFP = 1, hasNewValue = 1, opNewValue = 0 in
class T_MInstFloat <string mnemonic, bits<3> MajOp, bits<3> MinOp>
  : MInst<(outs IntRegs:$Rd),
          (ins IntRegs:$Rs, IntRegs:$Rt),
  "$Rd = "#mnemonic#"($Rs, $Rt)", [],
  "" , M_tc_3or4x_SLOT23 > ,
  Requires<[HasV5T]> {
    bits<5> Rd;
    bits<5> Rs;
    bits<5> Rt;

    let IClass = 0b1110;

    let Inst{27-24} = 0b1011;
    let Inst{23-21} = MajOp;
    let Inst{20-16} = Rs;
    let Inst{13} = 0b0;
    let Inst{12-8} = Rt;
    let Inst{7-5} = MinOp;
    let Inst{4-0} = Rd;
  }

let isCommutable = 1, isCodeGenOnly = 0 in {
  def F2_sfadd : T_MInstFloat < "sfadd", 0b000, 0b000>;
  def F2_sfmpy : T_MInstFloat < "sfmpy", 0b010, 0b000>;
}

let isCodeGenOnly = 0 in
def F2_sfsub : T_MInstFloat < "sfsub", 0b000, 0b001>;

def: Pat<(f32 (fadd F32:$src1, F32:$src2)),
         (F2_sfadd F32:$src1, F32:$src2)>;

def: Pat<(f32 (fsub F32:$src1, F32:$src2)),
         (F2_sfsub F32:$src1, F32:$src2)>;

def: Pat<(f32 (fmul F32:$src1, F32:$src2)),
         (F2_sfmpy F32:$src1, F32:$src2)>;

let Itinerary = M_tc_3x_SLOT23, isCodeGenOnly = 0 in {
  def F2_sfmax : T_MInstFloat < "sfmax", 0b100, 0b000>;
  def F2_sfmin : T_MInstFloat < "sfmin", 0b100, 0b001>;
}

let isCodeGenOnly = 0 in {
def F2_sffixupn : T_MInstFloat < "sffixupn", 0b110, 0b000>;
def F2_sffixupd : T_MInstFloat < "sffixupd", 0b110, 0b001>;
}

// F2_sfrecipa: Reciprocal approximation for division.
let isPredicateLate = 1, isFP = 1,
hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
def F2_sfrecipa: MInst <
  (outs IntRegs:$Rd, PredRegs:$Pe),
  (ins IntRegs:$Rs, IntRegs:$Rt),
  "$Rd, $Pe = sfrecipa($Rs, $Rt)">,
  Requires<[HasV5T]> {
    bits<5> Rd;
    bits<2> Pe;
    bits<5> Rs;
    bits<5> Rt;

    let IClass = 0b1110;
    let Inst{27-21} = 0b1011111;
    let Inst{20-16} = Rs;
    let Inst{13}    = 0b0;
    let Inst{12-8}  = Rt;
    let Inst{7}     = 0b1;
    let Inst{6-5}   = Pe;
    let Inst{4-0}   = Rd;
  }

// F2_dfcmpeq: Floating point compare for equal.
let isCompare = 1, isFP = 1 in
class T_fcmp <string mnemonic, RegisterClass RC, bits<3> MinOp,
              list<dag> pattern = [] >
  : ALU64Inst <(outs PredRegs:$dst), (ins RC:$src1, RC:$src2),
  "$dst = "#mnemonic#"($src1, $src2)", pattern,
  "" , ALU64_tc_2early_SLOT23 > ,
  Requires<[HasV5T]> {
    bits<2> dst;
    bits<5> src1;
    bits<5> src2;

    let IClass = 0b1101;

    let Inst{27-21} = 0b0010111;
    let Inst{20-16} = src1;
    let Inst{12-8}  = src2;
    let Inst{7-5}   = MinOp;
    let Inst{1-0}   = dst;
  }

class T_fcmp64 <string mnemonic, PatFrag OpNode, bits<3> MinOp>
  : T_fcmp <mnemonic, DoubleRegs, MinOp,
  [(set  I1:$dst, (OpNode F64:$src1, F64:$src2))]> {
  let IClass = 0b1101;
  let Inst{27-21} = 0b0010111;
}

class T_fcmp32 <string mnemonic, PatFrag OpNode, bits<3> MinOp>
  : T_fcmp <mnemonic, IntRegs, MinOp,
  [(set  I1:$dst, (OpNode F32:$src1, F32:$src2))]> {
  let IClass = 0b1100;
  let Inst{27-21} = 0b0111111;
}

let isCodeGenOnly = 0 in {
def F2_dfcmpeq : T_fcmp64<"dfcmp.eq", setoeq, 0b000>;
def F2_dfcmpgt : T_fcmp64<"dfcmp.gt", setogt, 0b001>;
def F2_dfcmpge : T_fcmp64<"dfcmp.ge", setoge, 0b010>;
def F2_dfcmpuo : T_fcmp64<"dfcmp.uo", setuo,  0b011>;

def F2_sfcmpge : T_fcmp32<"sfcmp.ge", setoge, 0b000>;
def F2_sfcmpuo : T_fcmp32<"sfcmp.uo", setuo,  0b001>;
def F2_sfcmpeq : T_fcmp32<"sfcmp.eq", setoeq, 0b011>;
def F2_sfcmpgt : T_fcmp32<"sfcmp.gt", setogt, 0b100>;
}

// F2 convert template classes:
let isFP = 1 in
class F2_RDD_RSS_CONVERT<string mnemonic, bits<3> MinOp,
                         SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
                         string chop ="">
  : SInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss),
   "$Rdd = "#mnemonic#"($Rss)"#chop,
   [(set RCOut:$Rdd, (Op RCIn:$Rss))], "",
   S_2op_tc_3or4x_SLOT23> {
     bits<5> Rdd;
     bits<5> Rss;

     let IClass = 0b1000;

     let Inst{27-21} = 0b0000111;
     let Inst{20-16} = Rss;
     let Inst{7-5} = MinOp;
     let Inst{4-0} = Rdd;
  }

let isFP = 1 in
class F2_RDD_RS_CONVERT<string mnemonic, bits<3> MinOp,
                        SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
                        string chop ="">
  : SInst <(outs DoubleRegs:$Rdd), (ins IntRegs:$Rs),
   "$Rdd = "#mnemonic#"($Rs)"#chop,
   [(set RCOut:$Rdd, (Op RCIn:$Rs))], "",
   S_2op_tc_3or4x_SLOT23> {
     bits<5> Rdd;
     bits<5> Rs;

     let IClass = 0b1000;

     let Inst{27-21} = 0b0100100;
     let Inst{20-16} = Rs;
     let Inst{7-5} = MinOp;
     let Inst{4-0} = Rdd;
  }

let isFP = 1, hasNewValue = 1 in
class F2_RD_RSS_CONVERT<string mnemonic, bits<3> MinOp,
                        SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
                        string chop ="">
  : SInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss),
   "$Rd = "#mnemonic#"($Rss)"#chop,
   [(set RCOut:$Rd, (Op RCIn:$Rss))], "",
   S_2op_tc_3or4x_SLOT23> {
     bits<5> Rd;
     bits<5> Rss;

     let IClass = 0b1000;

     let Inst{27-24} = 0b1000;
     let Inst{23-21} = MinOp;
     let Inst{20-16} = Rss;
     let Inst{7-5} = 0b001;
     let Inst{4-0} = Rd;
  }

let isFP = 1, hasNewValue = 1 in
class F2_RD_RS_CONVERT<string mnemonic, bits<3> MajOp, bits<3> MinOp,
                        SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
                        string chop ="">
  : SInst <(outs IntRegs:$Rd), (ins IntRegs:$Rs),
   "$Rd = "#mnemonic#"($Rs)"#chop,
   [(set RCOut:$Rd, (Op RCIn:$Rs))], "",
   S_2op_tc_3or4x_SLOT23> {
     bits<5> Rd;
     bits<5> Rs;

     let IClass = 0b1000;

     let Inst{27-24} = 0b1011;
     let Inst{23-21} = MajOp;
     let Inst{20-16} = Rs;
     let Inst{7-5} = MinOp;
     let Inst{4-0} = Rd;
  }

// Convert single precision to double precision and vice-versa.
let isCodeGenOnly = 0 in {
def F2_conv_sf2df : F2_RDD_RS_CONVERT <"convert_sf2df", 0b000,
                                       fextend, F64, F32>;

def F2_conv_df2sf : F2_RD_RSS_CONVERT <"convert_df2sf", 0b000,
                                       fround, F32, F64>;

// Convert Integer to Floating Point.
def F2_conv_d2sf : F2_RD_RSS_CONVERT <"convert_d2sf", 0b010,
                                       sint_to_fp, F32, I64>;
def F2_conv_ud2sf : F2_RD_RSS_CONVERT <"convert_ud2sf", 0b001,
                                       uint_to_fp, F32, I64>;
def F2_conv_uw2sf : F2_RD_RS_CONVERT <"convert_uw2sf", 0b001, 0b000,
                                       uint_to_fp, F32, I32>;
def F2_conv_w2sf : F2_RD_RS_CONVERT <"convert_w2sf", 0b010, 0b000,
                                       sint_to_fp, F32, I32>;
def F2_conv_d2df : F2_RDD_RSS_CONVERT <"convert_d2df", 0b011,
                                       sint_to_fp, F64, I64>;
def F2_conv_ud2df : F2_RDD_RSS_CONVERT <"convert_ud2df", 0b010,
                                        uint_to_fp, F64, I64>;
def F2_conv_uw2df : F2_RDD_RS_CONVERT <"convert_uw2df", 0b001,
                                       uint_to_fp, F64, I32>;
def F2_conv_w2df : F2_RDD_RS_CONVERT <"convert_w2df", 0b010,
                                       sint_to_fp, F64, I32>;

// Convert Floating Point to Integer - default.
def F2_conv_df2uw_chop : F2_RD_RSS_CONVERT <"convert_df2uw", 0b101,
                                            fp_to_uint, I32, F64, ":chop">;
def F2_conv_df2w_chop : F2_RD_RSS_CONVERT <"convert_df2w", 0b111,
                                            fp_to_sint, I32, F64, ":chop">;
def F2_conv_sf2uw_chop : F2_RD_RS_CONVERT <"convert_sf2uw", 0b011, 0b001,
                                       fp_to_uint, I32, F32, ":chop">;
def F2_conv_sf2w_chop : F2_RD_RS_CONVERT <"convert_sf2w", 0b100, 0b001,
                                       fp_to_sint, I32, F32, ":chop">;
def F2_conv_df2d_chop : F2_RDD_RSS_CONVERT <"convert_df2d", 0b110,
                                            fp_to_sint, I64, F64, ":chop">;
def F2_conv_df2ud_chop : F2_RDD_RSS_CONVERT <"convert_df2ud", 0b111,
                                             fp_to_uint, I64, F64, ":chop">;
def F2_conv_sf2d_chop : F2_RDD_RS_CONVERT <"convert_sf2d", 0b110,
                                       fp_to_sint, I64, F32, ":chop">;
def F2_conv_sf2ud_chop : F2_RDD_RS_CONVERT <"convert_sf2ud", 0b101,
                                            fp_to_uint, I64, F32, ":chop">;

// Convert Floating Point to Integer: non-chopped.
let AddedComplexity = 20, Predicates = [HasV5T, IEEERndNearV5T] in {
  def F2_conv_df2d : F2_RDD_RSS_CONVERT <"convert_df2d", 0b000,
                                         fp_to_sint, I64, F64>;
  def F2_conv_df2ud : F2_RDD_RSS_CONVERT <"convert_df2ud", 0b001,
                                          fp_to_uint, I64, F64>;
  def F2_conv_sf2ud : F2_RDD_RS_CONVERT <"convert_sf2ud", 0b011,
                                         fp_to_uint, I64, F32>;
  def F2_conv_sf2d : F2_RDD_RS_CONVERT <"convert_sf2d", 0b100,
                                         fp_to_sint, I64, F32>;
  def F2_conv_df2uw : F2_RD_RSS_CONVERT <"convert_df2uw", 0b011,
                                         fp_to_uint, I32, F64>;
  def F2_conv_df2w : F2_RD_RSS_CONVERT <"convert_df2w", 0b100,
                                         fp_to_sint, I32, F64>;
  def F2_conv_sf2uw : F2_RD_RS_CONVERT <"convert_sf2uw", 0b011, 0b000,
                                         fp_to_uint, I32, F32>;
  def F2_conv_sf2w : F2_RD_RS_CONVERT <"convert_sf2w", 0b100, 0b000,
                                         fp_to_sint, I32, F32>;
}
}

// Fix up radicand.
let isFP = 1, hasNewValue = 1, isCodeGenOnly = 0 in
def F2_sffixupr: SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs),
  "$Rd = sffixupr($Rs)",
  [], "" , S_2op_tc_3or4x_SLOT23>, Requires<[HasV5T]> {
    bits<5> Rd;
    bits<5> Rs;

    let IClass = 0b1000;

    let Inst{27-21} = 0b1011101;
    let Inst{20-16} = Rs;
    let Inst{7-5}   = 0b000;
    let Inst{4-0}   = Rd;
  }

// F2_sffma: Floating-point fused multiply add.
let isFP = 1, hasNewValue = 1 in
class T_sfmpy_acc <bit isSub, bit isLib>
  : MInst<(outs IntRegs:$Rx),
          (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
  "$Rx "#!if(isSub, "-=","+=")#" sfmpy($Rs, $Rt)"#!if(isLib, ":lib",""),
  [], "$dst2 = $Rx" , M_tc_3_SLOT23 > ,
  Requires<[HasV5T]> {
    bits<5> Rx;
    bits<5> Rs;
    bits<5> Rt;

    let IClass = 0b1110;

    let Inst{27-21} = 0b1111000;
    let Inst{20-16} = Rs;
    let Inst{13}    = 0b0;
    let Inst{12-8}  = Rt;
    let Inst{7}     = 0b1;
    let Inst{6}     = isLib;
    let Inst{5}     = isSub;
    let Inst{4-0}   = Rx;
  }

let isCodeGenOnly = 0 in {
def F2_sffma: T_sfmpy_acc <0, 0>;
def F2_sffms: T_sfmpy_acc <1, 0>;
def F2_sffma_lib: T_sfmpy_acc <0, 1>;
def F2_sffms_lib: T_sfmpy_acc <1, 1>;
}

// Floating-point fused multiply add w/ additional scaling (2**pu).
let isFP = 1, hasNewValue = 1, isCodeGenOnly = 0 in
def F2_sffma_sc: MInst <
  (outs IntRegs:$Rx),
  (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt, PredRegs:$Pu),
  "$Rx += sfmpy($Rs, $Rt, $Pu):scale" ,
  [], "$dst2 = $Rx" , M_tc_3_SLOT23 > ,
  Requires<[HasV5T]> {
    bits<5> Rx;
    bits<5> Rs;
    bits<5> Rt;
    bits<2> Pu;

    let IClass = 0b1110;

    let Inst{27-21} = 0b1111011;
    let Inst{20-16} = Rs;
    let Inst{13}    = 0b0;
    let Inst{12-8}  = Rt;
    let Inst{7}     = 0b1;
    let Inst{6-5}   = Pu;
    let Inst{4-0}   = Rx;
  }

let isExtended = 1, isExtentSigned = 1, opExtentBits = 8, opExtendable = 3,
    isPseudo = 1, InputType = "imm" in
def MUX_ir_f : ALU32_rr<(outs IntRegs:$dst),
      (ins PredRegs:$src1, IntRegs:$src2, f32Ext:$src3),
      "$dst = mux($src1, $src2, #$src3)",
      [(set F32:$dst, (f32 (select I1:$src1, F32:$src2, fpimm:$src3)))]>,
    Requires<[HasV5T]>;

let isExtended = 1, isExtentSigned = 1, opExtentBits = 8, opExtendable = 2,
    isPseudo = 1, InputType = "imm" in
def MUX_ri_f : ALU32_rr<(outs IntRegs:$dst),
      (ins PredRegs:$src1, f32Ext:$src2, IntRegs:$src3),
      "$dst = mux($src1, #$src2, $src3)",
      [(set F32:$dst, (f32 (select I1:$src1, fpimm:$src2, F32:$src3)))]>,
    Requires<[HasV5T]>;

// Classify floating-point value
let isFP = 1, isCodeGenOnly = 0 in
 def F2_sfclass : T_TEST_BIT_IMM<"sfclass", 0b111>;

let isFP = 1, isCodeGenOnly = 0 in
def F2_dfclass: ALU64Inst<(outs PredRegs:$Pd), (ins DoubleRegs:$Rss, u5Imm:$u5),
  "$Pd = dfclass($Rss, #$u5)",
  [], "" , ALU64_tc_2early_SLOT23 > , Requires<[HasV5T]> {
    bits<2> Pd;
    bits<5> Rss;
    bits<5> u5;

    let IClass = 0b1101;
    let Inst{27-21} = 0b1100100;
    let Inst{20-16} = Rss;
    let Inst{12-10} = 0b000;
    let Inst{9-5}   = u5;
    let Inst{4-3}   = 0b10;
    let Inst{1-0}   = Pd;
  }

// Instructions to create floating point constant
let hasNewValue = 1, opNewValue = 0 in
class T_fimm <string mnemonic, RegisterClass RC, bits<4> RegType, bit isNeg>
  : ALU64Inst<(outs RC:$dst), (ins u10Imm:$src),
  "$dst = "#mnemonic#"(#$src)"#!if(isNeg, ":neg", ":pos"),
  [], "", ALU64_tc_3x_SLOT23>, Requires<[HasV5T]> {
    bits<5> dst;
    bits<10> src;

    let IClass = 0b1101;
    let Inst{27-24} = RegType;
    let Inst{23}    = 0b0;
    let Inst{22}    = isNeg;
    let Inst{21}    = src{9};
    let Inst{13-5}  = src{8-0};
    let Inst{4-0}   = dst;
  }

let isCodeGenOnly = 0 in {
def F2_sfimm_p : T_fimm <"sfmake", IntRegs, 0b0110, 0>;
def F2_sfimm_n : T_fimm <"sfmake", IntRegs, 0b0110, 1>;
def F2_dfimm_p : T_fimm <"dfmake", DoubleRegs, 0b1001, 0>;
def F2_dfimm_n : T_fimm <"dfmake", DoubleRegs, 0b1001, 1>;
}

// olt.
def : Pat <(i1 (setolt (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
      (i1 (F2_sfcmpgt IntRegs:$src2, IntRegs:$src1))>,
      Requires<[HasV5T]>;

def : Pat <(i1 (setolt (f32 IntRegs:$src1), (fpimm:$src2))),
      (i1 (F2_sfcmpgt (f32 (TFRI_f fpimm:$src2)), (f32 IntRegs:$src1)))>,
      Requires<[HasV5T]>;

def : Pat <(i1 (setolt (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
      (i1 (F2_dfcmpgt DoubleRegs:$src2, DoubleRegs:$src1))>,
      Requires<[HasV5T]>;

def : Pat <(i1 (setolt (f64 DoubleRegs:$src1), (fpimm:$src2))),
      (i1 (F2_dfcmpgt (f64 (CONST64_Float_Real fpimm:$src2)),
                        (f64 DoubleRegs:$src1)))>,
      Requires<[HasV5T]>;

// gt.
def : Pat <(i1 (setugt (f64 DoubleRegs:$src1), (fpimm:$src2))),
      (i1 (F2_dfcmpgt (f64 DoubleRegs:$src1),
                        (f64 (CONST64_Float_Real fpimm:$src2))))>,
      Requires<[HasV5T]>;

def : Pat <(i1 (setugt (f32 IntRegs:$src1), (fpimm:$src2))),
      (i1 (F2_sfcmpgt (f32 IntRegs:$src1), (f32 (TFRI_f fpimm:$src2))))>,
      Requires<[HasV5T]>;

// ult.
def : Pat <(i1 (setult (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
      (i1 (F2_sfcmpgt IntRegs:$src2, IntRegs:$src1))>,
      Requires<[HasV5T]>;

def : Pat <(i1 (setult (f32 IntRegs:$src1), (fpimm:$src2))),
      (i1 (F2_sfcmpgt (f32 (TFRI_f fpimm:$src2)), (f32 IntRegs:$src1)))>,
      Requires<[HasV5T]>;

def : Pat <(i1 (setult (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
      (i1 (F2_dfcmpgt DoubleRegs:$src2, DoubleRegs:$src1))>,
      Requires<[HasV5T]>;

def : Pat <(i1 (setult (f64 DoubleRegs:$src1), (fpimm:$src2))),
      (i1 (F2_dfcmpgt (f64 (CONST64_Float_Real fpimm:$src2)),
                        (f64 DoubleRegs:$src1)))>,
      Requires<[HasV5T]>;

// le.
// rs <= rt -> rt >= rs.
def : Pat<(i1 (setole (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
      (i1 (F2_sfcmpge IntRegs:$src2, IntRegs:$src1))>,
      Requires<[HasV5T]>;

def : Pat<(i1 (setole (f32 IntRegs:$src1), (fpimm:$src2))),
      (i1 (F2_sfcmpge (f32 (TFRI_f fpimm:$src2)), IntRegs:$src1))>,
      Requires<[HasV5T]>;


// Rss <= Rtt -> Rtt >= Rss.
def : Pat<(i1 (setole (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
      (i1 (F2_dfcmpge DoubleRegs:$src2, DoubleRegs:$src1))>,
      Requires<[HasV5T]>;

def : Pat<(i1 (setole (f64 DoubleRegs:$src1), (fpimm:$src2))),
      (i1 (F2_dfcmpge (f64 (CONST64_Float_Real fpimm:$src2)),
                                DoubleRegs:$src1))>,
      Requires<[HasV5T]>;

// rs <= rt -> rt >= rs.
def : Pat<(i1 (setule (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
      (i1 (F2_sfcmpge IntRegs:$src2, IntRegs:$src1))>,
      Requires<[HasV5T]>;

def : Pat<(i1 (setule (f32 IntRegs:$src1), (fpimm:$src2))),
      (i1 (F2_sfcmpge (f32 (TFRI_f fpimm:$src2)), IntRegs:$src1))>,
      Requires<[HasV5T]>;

// Rss <= Rtt -> Rtt >= Rss.
def : Pat<(i1 (setule (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
      (i1 (F2_dfcmpge DoubleRegs:$src2, DoubleRegs:$src1))>,
      Requires<[HasV5T]>;

def : Pat<(i1 (setule (f64 DoubleRegs:$src1), (fpimm:$src2))),
      (i1 (F2_dfcmpge (f64 (CONST64_Float_Real fpimm:$src2)),
                                DoubleRegs:$src1))>,
      Requires<[HasV5T]>;

// ne.
def : Pat<(i1 (setone (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
      (i1 (C2_not (F2_sfcmpeq IntRegs:$src1, IntRegs:$src2)))>,
      Requires<[HasV5T]>;

def : Pat<(i1 (setone (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
      (i1 (C2_not (F2_dfcmpeq DoubleRegs:$src1, DoubleRegs:$src2)))>,
      Requires<[HasV5T]>;

def : Pat<(i1 (setune (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
      (i1 (C2_not (F2_sfcmpeq IntRegs:$src1, IntRegs:$src2)))>,
      Requires<[HasV5T]>;

def : Pat<(i1 (setune (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
      (i1 (C2_not (F2_dfcmpeq DoubleRegs:$src1, DoubleRegs:$src2)))>,
      Requires<[HasV5T]>;

def : Pat<(i1 (setone (f32 IntRegs:$src1), (fpimm:$src2))),
      (i1 (C2_not (F2_sfcmpeq IntRegs:$src1, (f32 (TFRI_f fpimm:$src2)))))>,
      Requires<[HasV5T]>;

def : Pat<(i1 (setone (f64 DoubleRegs:$src1), (fpimm:$src2))),
      (i1 (C2_not (F2_dfcmpeq DoubleRegs:$src1,
                              (f64 (CONST64_Float_Real fpimm:$src2)))))>,
      Requires<[HasV5T]>;

def : Pat<(i1 (setune (f32 IntRegs:$src1), (fpimm:$src2))),
      (i1 (C2_not (F2_sfcmpeq IntRegs:$src1,  (f32 (TFRI_f fpimm:$src2)))))>,
      Requires<[HasV5T]>;

def : Pat<(i1 (setune (f64 DoubleRegs:$src1), (fpimm:$src2))),
      (i1 (C2_not (F2_dfcmpeq DoubleRegs:$src1,
                              (f64 (CONST64_Float_Real fpimm:$src2)))))>,
      Requires<[HasV5T]>;

// Bitcast is different than [fp|sint|uint]_to_[sint|uint|fp].
def : Pat <(i32 (bitconvert (f32 IntRegs:$src))),
           (i32 (A2_tfr IntRegs:$src))>,
          Requires<[HasV5T]>;

def : Pat <(f32 (bitconvert (i32 IntRegs:$src))),
           (f32 (A2_tfr IntRegs:$src))>,
          Requires<[HasV5T]>;

def : Pat <(i64 (bitconvert (f64 DoubleRegs:$src))),
           (i64 (A2_tfrp DoubleRegs:$src))>,
          Requires<[HasV5T]>;

def : Pat <(f64 (bitconvert (i64 DoubleRegs:$src))),
           (f64 (A2_tfrp DoubleRegs:$src))>,
          Requires<[HasV5T]>;

def : Pat <(select (i1 (setult (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
                   (f32 IntRegs:$src3),
                   (f32 IntRegs:$src4)),
    (C2_mux (F2_sfcmpgt IntRegs:$src2, IntRegs:$src1), IntRegs:$src4,
                      IntRegs:$src3)>, Requires<[HasV5T]>;

def : Pat <(select (i1 (setult (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
                   (f64 DoubleRegs:$src3),
                   (f64 DoubleRegs:$src4)),
      (C2_vmux (F2_dfcmpgt DoubleRegs:$src2, DoubleRegs:$src1),
                DoubleRegs:$src4, DoubleRegs:$src3)>, Requires<[HasV5T]>;

// Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
// => r0 = TFR_condset_ri(p0, r1, #i)
def : Pat <(select (not PredRegs:$src1), fpimm:$src2, IntRegs:$src3),
      (MUX_ri_f PredRegs:$src1, IntRegs:$src3, fpimm:$src2)>;

// Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
// => r0 = TFR_condset_ir(p0, #i, r1)
def : Pat <(select (not PredRegs:$src1), IntRegs:$src2, fpimm:$src3),
      (MUX_ir_f PredRegs:$src1, fpimm:$src3, IntRegs:$src2)>;

def : Pat <(i32 (fp_to_sint (f64 DoubleRegs:$src1))),
          (i32 (EXTRACT_SUBREG (i64 (F2_conv_df2d_chop (f64 DoubleRegs:$src1))), subreg_loreg))>,
          Requires<[HasV5T]>;

def : Pat <(fabs (f32 IntRegs:$src1)),
           (S2_clrbit_i (f32 IntRegs:$src1), 31)>,
          Requires<[HasV5T]>;

def : Pat <(fneg (f32 IntRegs:$src1)),
           (S2_togglebit_i (f32 IntRegs:$src1), 31)>,
          Requires<[HasV5T]>;

/*
def : Pat <(fabs (f64 DoubleRegs:$src1)),
          (S2_clrbit_i (f32 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg)), 31)>,
          Requires<[HasV5T]>;

def : Pat <(fabs (f64 DoubleRegs:$src1)),
          (S2_clrbit_i (f32 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg)), 31)>,
          Requires<[HasV5T]>;
          */