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llvm-mirror/test/MC/RISCV/rv32zbb-valid.s

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[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92). It is implemented with each category of instruction as its own target feature, with the 'b' extension feature enabling all options. Since this extension is not yet ratified, all target features are prefixed with 'experimental-' to note their status. Differential Revision: https://reviews.llvm.org/D65649
2020-04-09 18:51:10 +02:00
# With B extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
[RISCV] Add rv64 run lines to rv32 MC layer tests for B extension Remove common instructions from rv64 tests since they are now covered by the rv64 run lines in the rv32 tests. Add rv32-only* tests for a few cases that aren't common between r32 and rv64. Addresses review feedback from D95150. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D95272
2021-01-27 02:03:21 +01:00
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92). It is implemented with each category of instruction as its own target feature, with the 'b' extension feature enabling all options. Since this extension is not yet ratified, all target features are prefixed with 'experimental-' to note their status. Differential Revision: https://reviews.llvm.org/D65649
2020-04-09 18:51:10 +02:00
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
[RISCV] Fix unused check prefixes in test/MC/RISCV/
2020-10-30 05:18:00 +01:00
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
[RISCV] Add rv64 run lines to rv32 MC layer tests for B extension Remove common instructions from rv64 tests since they are now covered by the rv64 run lines in the rv32 tests. Add rv32-only* tests for a few cases that aren't common between r32 and rv64. Addresses review feedback from D95150. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D95272
2021-01-27 02:03:21 +01:00
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92). It is implemented with each category of instruction as its own target feature, with the 'b' extension feature enabling all options. Since this extension is not yet ratified, all target features are prefixed with 'experimental-' to note their status. Differential Revision: https://reviews.llvm.org/D65649
2020-04-09 18:51:10 +02:00
# With Bitmanip base extension:
Revert "[RISCV] Remove -riscv-no-aliases in favour of new -M no-aliases" The replacement doesn't work for llc, but it is needed by patchable-function-entry.ll. This reverts commit aa9a30b83a06e3e5e68e32ea645ec2d9edc27efc.
2021-05-29 16:11:37 +02:00
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbb -riscv-no-aliases -show-encoding \
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92). It is implemented with each category of instruction as its own target feature, with the 'b' extension feature enabling all options. Since this extension is not yet ratified, all target features are prefixed with 'experimental-' to note their status. Differential Revision: https://reviews.llvm.org/D65649
2020-04-09 18:51:10 +02:00
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
Revert "[RISCV] Remove -riscv-no-aliases in favour of new -M no-aliases" The replacement doesn't work for llc, but it is needed by patchable-function-entry.ll. This reverts commit aa9a30b83a06e3e5e68e32ea645ec2d9edc27efc.
2021-05-29 16:11:37 +02:00
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbb -riscv-no-aliases -show-encoding \
[RISCV] Add rv64 run lines to rv32 MC layer tests for B extension Remove common instructions from rv64 tests since they are now covered by the rv64 run lines in the rv32 tests. Add rv32-only* tests for a few cases that aren't common between r32 and rv64. Addresses review feedback from D95150. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D95272
2021-01-27 02:03:21 +01:00
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92). It is implemented with each category of instruction as its own target feature, with the 'b' extension feature enabling all options. Since this extension is not yet ratified, all target features are prefixed with 'experimental-' to note their status. Differential Revision: https://reviews.llvm.org/D65649
2020-04-09 18:51:10 +02:00
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbb < %s \
[RISCV] Add zext.h instruction to Zbb. zext.h uses the same encoding as pack rd, rs, x0 in rv32 and packw rd, rs, x0 in rv64. Encodings without x0 as the second source are not valid in Zbb. I've added two new instructions with these specific encodings with predicates that enable them when either Zbb or Zbp is enabled. The pack spelling will only be accepted with Zbp. The disassembler will use the zext.h instruction when either feature is enabled. Using the pack spelling will print as pack when llvm-mc is emitting text. We could fix this with some custom code in processInstruction if this is important, but I'm not sure it is. Reviewed By: asb, frasercrmck Differential Revision: https://reviews.llvm.org/D94818
2021-01-22 20:58:03 +01:00
# RUN: | llvm-objdump --mattr=+experimental-zbb -M no-aliases -d -r - \
[RISCV] Fix unused check prefixes in test/MC/RISCV/
2020-10-30 05:18:00 +01:00
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
[RISCV] Add rv64 run lines to rv32 MC layer tests for B extension Remove common instructions from rv64 tests since they are now covered by the rv64 run lines in the rv32 tests. Add rv32-only* tests for a few cases that aren't common between r32 and rv64. Addresses review feedback from D95150. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D95272
2021-01-27 02:03:21 +01:00
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbb < %s \
# RUN: | llvm-objdump --mattr=+experimental-zbb -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92). It is implemented with each category of instruction as its own target feature, with the 'b' extension feature enabling all options. Since this extension is not yet ratified, all target features are prefixed with 'experimental-' to note their status. Differential Revision: https://reviews.llvm.org/D65649
2020-04-09 18:51:10 +02:00
# CHECK-ASM-AND-OBJ: clz t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0x03,0x60]
clz t0, t1
# CHECK-ASM-AND-OBJ: ctz t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0x13,0x60]
ctz t0, t1
[RISCV] Rename pcnt->cpop to match 0.93 bitmanip spec. This is the first of multiple patches to bring our 0.92 implementation up to 0.93. Reviewed By: asb, frasercrmck Differential Revision: https://reviews.llvm.org/D94568
2021-01-22 19:23:46 +01:00
# CHECK-ASM-AND-OBJ: cpop t0, t1
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92). It is implemented with each category of instruction as its own target feature, with the 'b' extension feature enabling all options. Since this extension is not yet ratified, all target features are prefixed with 'experimental-' to note their status. Differential Revision: https://reviews.llvm.org/D65649
2020-04-09 18:51:10 +02:00
# CHECK-ASM: encoding: [0x93,0x12,0x23,0x60]
[RISCV] Rename pcnt->cpop to match 0.93 bitmanip spec. This is the first of multiple patches to bring our 0.92 implementation up to 0.93. Reviewed By: asb, frasercrmck Differential Revision: https://reviews.llvm.org/D94568
2021-01-22 19:23:46 +01:00
cpop t0, t1
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92). It is implemented with each category of instruction as its own target feature, with the 'b' extension feature enabling all options. Since this extension is not yet ratified, all target features are prefixed with 'experimental-' to note their status. Differential Revision: https://reviews.llvm.org/D65649
2020-04-09 18:51:10 +02:00
# CHECK-ASM-AND-OBJ: sext.b t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0x43,0x60]
sext.b t0, t1
# CHECK-ASM-AND-OBJ: sext.h t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0x53,0x60]
sext.h t0, t1
# CHECK-ASM-AND-OBJ: min t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
min t0, t1, t2
# CHECK-ASM-AND-OBJ: minu t0, t1, t2
[RISCV] Swap encodings of max and minu to match 0.93 bitmanip spec. Reviewed By: asb, frasercrmck Differential Revision: https://reviews.llvm.org/D94580
2021-01-22 19:47:12 +01:00
# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x0a]
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92). It is implemented with each category of instruction as its own target feature, with the 'b' extension feature enabling all options. Since this extension is not yet ratified, all target features are prefixed with 'experimental-' to note their status. Differential Revision: https://reviews.llvm.org/D65649
2020-04-09 18:51:10 +02:00
minu t0, t1, t2
[RISCV] Swap encodings of max and minu to match 0.93 bitmanip spec. Reviewed By: asb, frasercrmck Differential Revision: https://reviews.llvm.org/D94580
2021-01-22 19:47:12 +01:00
# CHECK-ASM-AND-OBJ: max t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
max t0, t1, t2
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92). It is implemented with each category of instruction as its own target feature, with the 'b' extension feature enabling all options. Since this extension is not yet ratified, all target features are prefixed with 'experimental-' to note their status. Differential Revision: https://reviews.llvm.org/D65649
2020-04-09 18:51:10 +02:00
# CHECK-ASM-AND-OBJ: maxu t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x72,0x73,0x0a]
maxu t0, t1, t2
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