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125 lines
5.9 KiB
TableGen
125 lines
5.9 KiB
TableGen
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//===- AArch64SchedPredExynos.td - AArch64 Sched Preds -----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines scheduling predicate definitions that are used by the
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// AArch64 Exynos processors.
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//
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//===----------------------------------------------------------------------===//
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// Identify BLR specifying the LR register as the indirect target register.
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def ExynosBranchLinkLRPred : MCSchedPredicate<
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CheckAll<[CheckOpcode<[BLR]>,
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CheckRegOperand<0, LR>]>>;
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// Identify arithmetic and logic instructions without or with limited extension.
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def ExynosExtFn : TIIPredicate<
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"isExynosExtFast",
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MCOpcodeSwitchStatement<
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[MCOpcodeSwitchCase<
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IsArithExt32Op.ValidOpcodes,
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MCReturnStatement<
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CheckAny<[CheckExtBy0,
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CheckAll<
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[CheckExtUXTW,
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CheckAny<
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[CheckExtBy1,
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CheckExtBy2,
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CheckExtBy3]>]>]>>>,
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MCOpcodeSwitchCase<
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IsArithExt64Op.ValidOpcodes,
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MCReturnStatement<
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CheckAny<[CheckExtBy0,
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CheckAll<
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[CheckExtUXTX,
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CheckAny<
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[CheckExtBy1,
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CheckExtBy2,
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CheckExtBy3]>]>]>>>],
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MCReturnStatement<FalsePred>>>;
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def ExynosExtPred : MCSchedPredicate<ExynosExtFn>;
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// Identify FP instructions.
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def ExynosFPPred : MCSchedPredicate<CheckAny<[CheckDForm, CheckQForm]>>;
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// Identify whether an instruction whose result is a long vector
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// operates on the upper half of the input registers.
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def ExynosLongVectorUpperFn : TIIPredicate<
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"isExynosLongVectorUpper",
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MCOpcodeSwitchStatement<
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[MCOpcodeSwitchCase<
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IsLongVectorUpperOp.ValidOpcodes,
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MCReturnStatement<TruePred>>],
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MCReturnStatement<FalsePred>>>;
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def ExynosLongVectorUpperPred : MCSchedPredicate<ExynosLongVectorUpperFn>;
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// Identify 128-bit NEON instructions.
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def ExynosQFormPred : MCSchedPredicate<CheckQForm>;
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// Identify instructions that reset a register efficiently.
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def ExynosResetFn : TIIPredicate<
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"isExynosResetFast",
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MCOpcodeSwitchStatement<
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[MCOpcodeSwitchCase<
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[ADR, ADRP,
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MOVNWi, MOVNXi,
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MOVZWi, MOVZXi],
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MCReturnStatement<TruePred>>],
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MCReturnStatement<
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CheckAny<
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[IsCopyIdiomFn,
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IsZeroFPIdiomFn,
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IsZeroIdiomFn]>>>>;
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def ExynosResetPred : MCSchedPredicate<ExynosResetFn>;
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// Identify EXTR as the alias for ROR (immediate).
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def ExynosRotateRightImmPred : MCSchedPredicate<
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CheckAll<[CheckOpcode<[EXTRWrri, EXTRXrri]>,
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CheckSameRegOperand<1, 2>]>>;
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// Identify arithmetic and logic instructions without or with limited shift.
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def ExynosShiftFn : TIIPredicate<
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"isExynosShiftFast",
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MCOpcodeSwitchStatement<
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[MCOpcodeSwitchCase<
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IsArithLogicShiftOp.ValidOpcodes,
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MCReturnStatement<
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CheckAny<[CheckShiftBy0,
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CheckAll<
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[CheckShiftLSL,
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CheckAny<
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[CheckShiftBy1,
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CheckShiftBy2,
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CheckShiftBy3]>]>]>>>],
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MCReturnStatement<FalsePred>>>;
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def ExynosShiftPred : MCSchedPredicate<ExynosShiftFn>;
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// Identify more arithmetic and logic instructions without or limited shift.
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def ExynosShiftExFn : TIIPredicate<
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"isExynosShiftExFast",
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MCOpcodeSwitchStatement<
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[MCOpcodeSwitchCase<
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IsArithLogicShiftOp.ValidOpcodes,
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MCReturnStatement<
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CheckAll<
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[CheckShiftLSL,
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CheckShiftBy8]>>>],
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MCReturnStatement<ExynosShiftFn>>>;
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def ExynosShiftExPred : MCSchedPredicate<ExynosShiftExFn>;
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// Identify arithmetic and logic immediate instructions.
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def ExynosCheapFn : TIIPredicate<
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"isExynosCheapAsMove",
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MCOpcodeSwitchStatement<
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[MCOpcodeSwitchCase<
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IsArithLogicImmOp.ValidOpcodes,
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MCReturnStatement<TruePred>>],
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MCReturnStatement<
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CheckAny<
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[ExynosExtFn, ExynosResetFn, ExynosShiftFn]>>>>;
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