llvm-mirror/lib/Target/CellSPU/CMakeLists.txt

set(LLVM_TARGET_DEFINITIONS SPU.td)

tablegen(SPUGenInstrNames.inc -gen-instr-enums)
tablegen(SPUGenRegisterNames.inc -gen-register-enums)
tablegen(SPUGenAsmWriter.inc -gen-asm-writer)
tablegen(SPUGenCodeEmitter.inc -gen-emitter)
tablegen(SPUGenRegisterInfo.h.inc -gen-register-desc-header)
tablegen(SPUGenRegisterInfo.inc -gen-register-desc)
tablegen(SPUGenInstrInfo.inc -gen-instr-desc)
tablegen(SPUGenDAGISel.inc -gen-dag-isel)
tablegen(SPUGenSubtarget.inc -gen-subtarget)
tablegen(SPUGenCallingConv.inc -gen-callingconv)

add_llvm_target(CellSPUCodeGen
  SPUAsmPrinter.cpp
  SPUHazardRecognizers.cpp
  SPUInstrInfo.cpp
  SPUISelDAGToDAG.cpp
  SPUISelLowering.cpp
  SPUFrameLowering.cpp
  SPUMCAsmInfo.cpp
  SPURegisterInfo.cpp
  SPUSubtarget.cpp
  SPUTargetMachine.cpp
  SPUSelectionDAGInfo.cpp
  SPUNopFiller.cpp
  )
CMake: Builds all targets. llvm-svn: 56641 2008-09-26 06:40:32 +02:00			`set(LLVM_TARGET_DEFINITIONS SPU.td)`

			`tablegen(SPUGenInstrNames.inc -gen-instr-enums)`
			`tablegen(SPUGenRegisterNames.inc -gen-register-enums)`
			`tablegen(SPUGenAsmWriter.inc -gen-asm-writer)`
			`tablegen(SPUGenCodeEmitter.inc -gen-emitter)`
			`tablegen(SPUGenRegisterInfo.h.inc -gen-register-desc-header)`
			`tablegen(SPUGenRegisterInfo.inc -gen-register-desc)`
			`tablegen(SPUGenInstrInfo.inc -gen-instr-desc)`
			`tablegen(SPUGenDAGISel.inc -gen-dag-isel)`
			`tablegen(SPUGenSubtarget.inc -gen-subtarget)`
			`tablegen(SPUGenCallingConv.inc -gen-callingconv)`

CMake: Reflected changes on the CellSPU target build. May require a clean start. llvm-svn: 58924 2008-11-08 21:37:19 +01:00			`add_llvm_target(CellSPUCodeGen`
move all the target's asmprinters into the main target. The piece that should be split out is the InstPrinter (if a target is mc'ized). This change makes all the targets be consistent. llvm-svn: 119056 2010-11-14 19:43:56 +01:00			`SPUAsmPrinter.cpp`
CMake: Builds all targets. llvm-svn: 56641 2008-09-26 06:40:32 +02:00			`SPUHazardRecognizers.cpp`
			`SPUInstrInfo.cpp`
			`SPUISelDAGToDAG.cpp`
			`SPUISelLowering.cpp`
Update CMake stuff llvm-svn: 123171 2011-01-10 13:39:23 +01:00			`SPUFrameLowering.cpp`
Normalize makefile comments and sort cmake file lists. llvm-svn: 80584 2009-08-31 15:05:24 +02:00			`SPUMCAsmInfo.cpp`
CMake: Builds all targets. llvm-svn: 56641 2008-09-26 06:40:32 +02:00			`SPURegisterInfo.cpp`
			`SPUSubtarget.cpp`
			`SPUTargetMachine.cpp`
Add skeleton target-specific SelectionDAGInfo files. llvm-svn: 101564 2010-04-17 01:04:22 +02:00			`SPUSelectionDAGInfo.cpp`
Add a "nop filler" pass to SPU. Filling no-ops is done just before emitting of assembly, when the instruction stream is final. No-ops are inserted to align the instructions so the dual-issue of the pipeline is utilized. This speeds up generated code with a minimum of 1% on a select set of algorithms. This pass may be redundant if the instruction scheduler and all subsequent passes that modify the instruction stream (prolog+epilog inserter, register scavenger, are there others?) are made aware of the instruction alignments. llvm-svn: 123226 2011-01-11 10:07:54 +01:00			`SPUNopFiller.cpp`
CMake: Builds all targets. llvm-svn: 56641 2008-09-26 06:40:32 +02:00			`)`