llvm-mirror/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt

# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {invalid instruction encoding}
# XFAIL: *

# Opcode=1934 Name=t2LDREXD Format=ARM_FORMAT_THUMBFRM(25)
#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 1| 0: 0: 1: 0| 1: 0: 0: 0| 1: 0: 0: 0| 0: 1: 1: 1| 1: 1: 1: 1|
# -------------------------------------------------------------------------------------------------
# 
# if t == t2 then UNPREDICTABLE
0xd2 0xe8 0x7f 0x88
Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. llvm-svn: 139250 2011-09-07 21:42:28 +02:00			`# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 \|& grep {invalid instruction encoding}`
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144 2011-08-09 22:55:18 +02:00			`# XFAIL: *`
Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations. llvm-svn: 129531 2011-04-14 21:13:28 +02:00
			`# Opcode=1934 Name=t2LDREXD Format=ARM_FORMAT_THUMBFRM(25)`
			`# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0`
			`# -------------------------------------------------------------------------------------------------`
			`# \| 1: 1: 1: 0\| 1: 0: 0: 0\| 1: 1: 0: 1\| 0: 0: 1: 0\| 1: 0: 0: 0\| 1: 0: 0: 0\| 0: 1: 1: 1\| 1: 1: 1: 1\|`
			`# -------------------------------------------------------------------------------------------------`
			`#`
			`# if t == t2 then UNPREDICTABLE`
			`0xd2 0xe8 0x7f 0x88`