RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 11:13:28 +01:00
Code Issues Projects Releases Wiki Activity
cf4816b501
llvm-mirror/test/MC/RISCV/fixups.s

84 lines
2.7 KiB
ArmAsm
Raw Normal View History

[RISCV] Enable emission of alias instructions by default This patch switches the default for -riscv-no-aliases to false and updates all affected MC and CodeGen tests. As recommended in D41071, MC tests use the canonical instructions and the CodeGen tests use the aliases. Additionally, for the f and d instructions with rounding mode, the tests for the aliased versions are moved and tightened such that they can actually detect if alias emission is enabled. (see D40902 for context) Differential Revision: https://reviews.llvm.org/D41225 Patch by Mario Werner. llvm-svn: 320797
2017-12-15 10:47:01 +01:00
# RUN: llvm-mc -triple riscv32 -riscv-no-aliases < %s -show-encoding \
[RISCV] Add common fixups and relocations %lo(), %hi(), and %pcrel_hi() are supported and test cases have been added to ensure the appropriate fixups and relocations are generated. I've added an instruction format field which is used in RISCVMCCodeEmitter to, for instance, tell whether it should emit a lo12_i fixup or a lo12_s fixup (RISC-V has two 12-bit immediate encodings depending on the instruction type). Differential Revision: https://reviews.llvm.org/D23568 llvm-svn: 314389
2017-09-28 10:26:24 +02:00
# RUN: | FileCheck -check-prefix=CHECK-FIXUP %s
# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
[RISCV] Support llvm-objdump -M no-aliases and -M numeric Summary: Now that llvm-objdump allows target-specific options, we match the `no-aliases` and `numeric` options for RISC-V, as supported by GNU objdump. This is done by overriding the variables used for the command-line options, so that the command-line options are still supported. This patch updates all tests using `llvm-objdump -riscv-no-aliases` to use `llvm-objdump -M no-aliases`. Reviewers: luismarques, asb Reviewed By: luismarques, asb Subscribers: pzheng, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66139 llvm-svn: 371534
2019-09-10 18:24:03 +02:00
# RUN: | llvm-objdump -M no-aliases -d - \
[RISCV] Enable emission of alias instructions by default This patch switches the default for -riscv-no-aliases to false and updates all affected MC and CodeGen tests. As recommended in D41071, MC tests use the canonical instructions and the CodeGen tests use the aliases. Additionally, for the f and d instructions with rounding mode, the tests for the aliased versions are moved and tightened such that they can actually detect if alias emission is enabled. (see D40902 for context) Differential Revision: https://reviews.llvm.org/D41225 Patch by Mario Werner. llvm-svn: 320797
2017-12-15 10:47:01 +01:00
# RUN: | FileCheck -check-prefix=CHECK-INSTR %s
[RISCV] Add common fixups and relocations %lo(), %hi(), and %pcrel_hi() are supported and test cases have been added to ensure the appropriate fixups and relocations are generated. I've added an instruction format field which is used in RISCVMCCodeEmitter to, for instance, tell whether it should emit a lo12_i fixup or a lo12_s fixup (RISC-V has two 12-bit immediate encodings depending on the instruction type). Differential Revision: https://reviews.llvm.org/D23568 llvm-svn: 314389
2017-09-28 10:26:24 +02:00
# RUN: llvm-mc -filetype=obj -triple=riscv32 %s \
[llvm-readobj] Update tests because of changes in llvm-readobj behavior This patch updates tests using llvm-readobj and llvm-readelf, because soon reading from stdin will be achievable only via a '-' as described here: https://bugs.llvm.org/show_bug.cgi?id=46400. Patch with changes to llvm-readobj behavior is here: https://reviews.llvm.org/D83704 Differential Revision: https://reviews.llvm.org/D83912 Reviewed by: jhenderson, MaskRay, grimar
2020-07-20 09:39:14 +02:00
# RUN: | llvm-readobj -r - | FileCheck %s -check-prefix=CHECK-REL
[RISCV] Add common fixups and relocations %lo(), %hi(), and %pcrel_hi() are supported and test cases have been added to ensure the appropriate fixups and relocations are generated. I've added an instruction format field which is used in RISCVMCCodeEmitter to, for instance, tell whether it should emit a lo12_i fixup or a lo12_s fixup (RISC-V has two 12-bit immediate encodings depending on the instruction type). Differential Revision: https://reviews.llvm.org/D23568 llvm-svn: 314389
2017-09-28 10:26:24 +02:00
# Checks that fixups that can be resolved within the same object file are
# applied correctly
.LBB0:
lui t1, %hi(val)
# CHECK-FIXUP: fixup A - offset: 0, value: %hi(val), kind: fixup_riscv_hi20
# CHECK-INSTR: lui t1, 74565
lw a0, %lo(val)(t1)
# CHECK-FIXUP: fixup A - offset: 0, value: %lo(val), kind: fixup_riscv_lo12_i
# CHECK-INSTR: lw a0, 1656(t1)
addi a1, t1, %lo(val)
# CHECK-FIXUP: fixup A - offset: 0, value: %lo(val), kind: fixup_riscv_lo12_i
# CHECK-INSTR: addi a1, t1, 1656
sw a0, %lo(val)(t1)
# CHECK-FIXUP: fixup A - offset: 0, value: %lo(val), kind: fixup_riscv_lo12_s
# CHECK-INSTR: sw a0, 1656(t1)
[RISCV] Properly evaluate fixup_riscv_pcrel_lo12 This is a update to D43157 to correctly handle fixup_riscv_pcrel_lo12. Notable changes: Rebased onto trunk Handle and test S-type Test case pcrel-hilo.s is merged into relocations.s D43157 description: VK_RISCV_PCREL_LO has to be handled specially. The MCExpr inside is actually the location of an auipc instruction with a VK_RISCV_PCREL_HI fixup pointing to the real target. Differential Revision: https://reviews.llvm.org/D54029 Patch by Chih-Mao Chen and Michael Spencer. llvm-svn: 349764
2018-12-20 15:52:15 +01:00
1:
auipc t1, %pcrel_hi(.LBB0)
# CHECK-FIXUP: fixup A - offset: 0, value: %pcrel_hi(.LBB0), kind: fixup_riscv_pcrel_hi20
# CHECK-INSTR: auipc t1, 0
addi t1, t1, %pcrel_lo(1b)
# CHECK-FIXUP: fixup A - offset: 0, value: %pcrel_lo(.Ltmp0), kind: fixup_riscv_pcrel_lo12_i
# CHECK-INSTR: addi t1, t1, -16
sw t1, %pcrel_lo(1b)(t1)
# CHECK-FIXUP: fixup A - offset: 0, value: %pcrel_lo(.Ltmp0), kind: fixup_riscv_pcrel_lo12_s
# CHECK-INSTR: sw t1, -16(t1)
[RISCV] Add common fixups and relocations %lo(), %hi(), and %pcrel_hi() are supported and test cases have been added to ensure the appropriate fixups and relocations are generated. I've added an instruction format field which is used in RISCVMCCodeEmitter to, for instance, tell whether it should emit a lo12_i fixup or a lo12_s fixup (RISC-V has two 12-bit immediate encodings depending on the instruction type). Differential Revision: https://reviews.llvm.org/D23568 llvm-svn: 314389
2017-09-28 10:26:24 +02:00
jal zero, .LBB0
# CHECK-FIXUP: fixup A - offset: 0, value: .LBB0, kind: fixup_riscv_jal
[RISCV] Properly evaluate fixup_riscv_pcrel_lo12 This is a update to D43157 to correctly handle fixup_riscv_pcrel_lo12. Notable changes: Rebased onto trunk Handle and test S-type Test case pcrel-hilo.s is merged into relocations.s D43157 description: VK_RISCV_PCREL_LO has to be handled specially. The MCExpr inside is actually the location of an auipc instruction with a VK_RISCV_PCREL_HI fixup pointing to the real target. Differential Revision: https://reviews.llvm.org/D54029 Patch by Chih-Mao Chen and Michael Spencer. llvm-svn: 349764
2018-12-20 15:52:15 +01:00
# CHECK-INSTR: jal zero, -28
[RISCV] Add common fixups and relocations %lo(), %hi(), and %pcrel_hi() are supported and test cases have been added to ensure the appropriate fixups and relocations are generated. I've added an instruction format field which is used in RISCVMCCodeEmitter to, for instance, tell whether it should emit a lo12_i fixup or a lo12_s fixup (RISC-V has two 12-bit immediate encodings depending on the instruction type). Differential Revision: https://reviews.llvm.org/D23568 llvm-svn: 314389
2017-09-28 10:26:24 +02:00
jal zero, .LBB2
# CHECK-FIXUP: fixup A - offset: 0, value: .LBB2, kind: fixup_riscv_jal
# CHECK-INSTR: jal zero, 330996
beq a0, a1, .LBB0
# CHECK-FIXUP: fixup A - offset: 0, value: .LBB0, kind: fixup_riscv_branch
[RISCV] Properly evaluate fixup_riscv_pcrel_lo12 This is a update to D43157 to correctly handle fixup_riscv_pcrel_lo12. Notable changes: Rebased onto trunk Handle and test S-type Test case pcrel-hilo.s is merged into relocations.s D43157 description: VK_RISCV_PCREL_LO has to be handled specially. The MCExpr inside is actually the location of an auipc instruction with a VK_RISCV_PCREL_HI fixup pointing to the real target. Differential Revision: https://reviews.llvm.org/D54029 Patch by Chih-Mao Chen and Michael Spencer. llvm-svn: 349764
2018-12-20 15:52:15 +01:00
# CHECK-INSTR: beq a0, a1, -36
[RISCV] Add common fixups and relocations %lo(), %hi(), and %pcrel_hi() are supported and test cases have been added to ensure the appropriate fixups and relocations are generated. I've added an instruction format field which is used in RISCVMCCodeEmitter to, for instance, tell whether it should emit a lo12_i fixup or a lo12_s fixup (RISC-V has two 12-bit immediate encodings depending on the instruction type). Differential Revision: https://reviews.llvm.org/D23568 llvm-svn: 314389
2017-09-28 10:26:24 +02:00
blt a0, a1, .LBB1
# CHECK-FIXUP: fixup A - offset: 0, value: .LBB1, kind: fixup_riscv_branch
# CHECK-INSTR: blt a0, a1, 1108
.fill 1104
.LBB1:
.fill 329876
addi zero, zero, 0
.LBB2:
.set val, 0x12345678
# CHECK-REL-NOT: R_RISCV
[RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table Resolving fixup_riscv_call by assembler when the linker relaxation diabled and the function and callsite within the same compile unit. And also adding static_assert after Infos array declaration to avoid missing any new fixup in MCFixupKindInfo in the future. Differential Revision: https://reviews.llvm.org/D47126 llvm-svn: 333487
2018-05-30 03:16:36 +02:00
[RISCV][NFC] Trivial cleanup Fix a typo. Remove two seemingly out-of-date TODO comments.
2019-12-17 12:42:32 +01:00
# Testing the function call offset could resolved by assembler
[RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table Resolving fixup_riscv_call by assembler when the linker relaxation diabled and the function and callsite within the same compile unit. And also adding static_assert after Infos array declaration to avoid missing any new fixup in MCFixupKindInfo in the future. Differential Revision: https://reviews.llvm.org/D47126 llvm-svn: 333487
2018-05-30 03:16:36 +02:00
# when the function and the callsite within the same compile unit
# and the linker relaxation is disabled.
func:
.fill 100
call func
# CHECK-FIXUP: fixup A - offset: 0, value: func, kind: fixup_riscv_call
# CHECK-INSTR: auipc ra, 0
[RISCV] Match GNU tools canonical JALR and add aliases The canonical GNU form of JALR resembles a load/store instruction rather than placing the immediate offset as a separate argument, so match this behaviour. Also add parser-only aliases for the three-operand form, and add other shorter aliases also emitted by GNU tools. Differential Revision: https://reviews.llvm.org/D55277 Patch by James Clarke. llvm-svn: 366179
2019-07-16 06:56:43 +02:00
# CHECK-INSTR: jalr ra, -100(ra)
[RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table Resolving fixup_riscv_call by assembler when the linker relaxation diabled and the function and callsite within the same compile unit. And also adding static_assert after Infos array declaration to avoid missing any new fixup in MCFixupKindInfo in the future. Differential Revision: https://reviews.llvm.org/D47126 llvm-svn: 333487
2018-05-30 03:16:36 +02:00
.fill 10000
call func
# CHECK-FIXUP: fixup A - offset: 0, value: func, kind: fixup_riscv_call
# CHECK-INSTR: auipc ra, 1048574
[RISCV] Match GNU tools canonical JALR and add aliases The canonical GNU form of JALR resembles a load/store instruction rather than placing the immediate offset as a separate argument, so match this behaviour. Also add parser-only aliases for the three-operand form, and add other shorter aliases also emitted by GNU tools. Differential Revision: https://reviews.llvm.org/D55277 Patch by James Clarke. llvm-svn: 366179
2019-07-16 06:56:43 +02:00
# CHECK-INSTR: jalr ra, -1916(ra)
[RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table Resolving fixup_riscv_call by assembler when the linker relaxation diabled and the function and callsite within the same compile unit. And also adding static_assert after Infos array declaration to avoid missing any new fixup in MCFixupKindInfo in the future. Differential Revision: https://reviews.llvm.org/D47126 llvm-svn: 333487
2018-05-30 03:16:36 +02:00
.fill 20888
call func
# CHECK-FIXUP: fixup A - offset: 0, value: func, kind: fixup_riscv_call
# CHECK-INSTR: auipc ra, 1048568
[RISCV] Match GNU tools canonical JALR and add aliases The canonical GNU form of JALR resembles a load/store instruction rather than placing the immediate offset as a separate argument, so match this behaviour. Also add parser-only aliases for the three-operand form, and add other shorter aliases also emitted by GNU tools. Differential Revision: https://reviews.llvm.org/D55277 Patch by James Clarke. llvm-svn: 366179
2019-07-16 06:56:43 +02:00
# CHECK-INSTR: jalr ra, 1764(ra)
Reference in New Issue Copy Permalink