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llvm-mirror/test/MC/RISCV/rv32d-invalid.s

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[RISCV] MC layer support for the standard RV32D instruction set extension As the FPR32 and FPR64 registers have the same names, use validateTargetOperandClass in RISCVAsmParser to coerce a parsed FPR32 to an FPR64 when necessary. The rest of this patch is very similar to the RV32F patch. Differential Revision: https://reviews.llvm.org/D39895 llvm-svn: 320023
2017-12-07 11:46:23 +01:00
# RUN: not llvm-mc -triple riscv32 -mattr=+d < %s 2>&1 | FileCheck %s
# Out of range immediates
## simm12
[RISCV] Support assembling TLS add and associated modifiers This patch adds support in the MC layer for parsing and assembling the 4-operand add instruction needed for TLS addressing. This also involves parsing the %tprel_hi, %tprel_lo and %tprel_add operand modifiers. Differential Revision: https://reviews.llvm.org/D55341 llvm-svn: 357698
2019-04-04 16:13:37 +02:00
fld ft1, -2049(a0) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
fsd ft2, 2048(a1) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
[RISCV] MC layer support for the standard RV32D instruction set extension As the FPR32 and FPR64 registers have the same names, use validateTargetOperandClass in RISCVAsmParser to coerce a parsed FPR32 to an FPR64 when necessary. The rest of this patch is very similar to the RV32F patch. Differential Revision: https://reviews.llvm.org/D39895 llvm-svn: 320023
2017-12-07 11:46:23 +01:00
# Memory operand not formatted correctly
[RISCV] Implement pseudo instructions for load/store from a symbol address. Summary: Those pseudo-instructions are making load/store instructions able to load/store from/to a symbol, and its always using PC-relative addressing to generating a symbol address. Reviewers: asb, apazos, rogfer01, jrtc27 Differential Revision: https://reviews.llvm.org/D50496 llvm-svn: 354430
2019-02-20 04:31:32 +01:00
fld ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
fsd ft2, a1, 100 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
[RISCV] MC layer support for the standard RV32D instruction set extension As the FPR32 and FPR64 registers have the same names, use validateTargetOperandClass in RISCVAsmParser to coerce a parsed FPR32 to an FPR64 when necessary. The rest of this patch is very similar to the RV32F patch. Differential Revision: https://reviews.llvm.org/D39895 llvm-svn: 320023
2017-12-07 11:46:23 +01:00
# Invalid register names
fld ft15, 100(a0) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
fld ft1, 100(a10) # CHECK: :[[@LINE]]:14: error: expected register
fsgnjn.d fa100, fa2, fa3 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
# Integer registers where FP regs are expected
fadd.d a2, a1, a0 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
# FP registers where integer regs are expected
fcvt.wu.d ft2, a1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
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