llvm-mirror/test/CodeGen/X86/rem-2.ll

mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 04:02:41 +01:00
; RUN: llc < %s -march=x86 | not grep cltd

define i32 @test(i32 %X) nounwind readnone {
entry:
	%0 = srem i32 41, %X
	ret i32 %0
}
Eliminate more uses of llvm-as and llvm-dis. llvm-svn: 81290 2009-09-09 01:54:48 +02:00			`; RUN: llc < %s -march=x86 \| not grep cltd`
DIVREM isel deficiency: If sign bit is known zero, zero out DX/EDX/RDX instead of sign extending the low part (in AX/EAX/RAX) into it. llvm-svn: 62519 2009-01-19 20:06:11 +01:00
			`define i32 @test(i32 %X) nounwind readnone {`
			`entry:`
			`%0 = srem i32 41, %X`
			`ret i32 %0`
			`}`