llvm-mirror/test/MC/RISCV/priv-invalid.s

# RUN: not llvm-mc -triple riscv32 < %s 2>&1 | FileCheck %s

mret 0x10 # CHECK: :[[@LINE]]:6: error: invalid operand for instruction

sfence.vma zero, a1, a2 # CHECK: :[[@LINE]]:22: error: invalid operand for instruction

sfence.vma a0, 0x10 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
[RISCV] MC layer support for the instructions added in the privileged spec Adds support for the instructions added in the RISC-V privileged ISA (https://content.riscv.org/wp-content/uploads/2017/05/riscv-privileged-v1.10.pdf): uret, sret, mret, wfi, and sfence.vma. Note from the committer: I made very minor formatting changes prior to commit, which didn't seem worth creating another review round-trip for. Differential Revision: https://reviews.llvm.org/D40383 Patch by David Craven. llvm-svn: 320484 2017-12-12 16:17:45 +01:00			`# RUN: not llvm-mc -triple riscv32 < %s 2>&1 \| FileCheck %s`

			`mret 0x10 # CHECK: :[[@LINE]]:6: error: invalid operand for instruction`

[RISCV] Define sfence.vma InstAliases to match the GNU RISC-V tools Unfortunately these aren't defined explicitly in the privileged spec, but the GNU assembler does accept `sfence.vma` and `sfence.vma rs` as well as the usual `sfence.vma rs, rt`. llvm-svn: 320575 2017-12-13 13:46:55 +01:00			`sfence.vma zero, a1, a2 # CHECK: :[[@LINE]]:22: error: invalid operand for instruction`
[RISCV] MC layer support for the instructions added in the privileged spec Adds support for the instructions added in the RISC-V privileged ISA (https://content.riscv.org/wp-content/uploads/2017/05/riscv-privileged-v1.10.pdf): uret, sret, mret, wfi, and sfence.vma. Note from the committer: I made very minor formatting changes prior to commit, which didn't seem worth creating another review round-trip for. Differential Revision: https://reviews.llvm.org/D40383 Patch by David Craven. llvm-svn: 320484 2017-12-12 16:17:45 +01:00
			`sfence.vma a0, 0x10 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction`