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269 lines
8.5 KiB
C++
269 lines
8.5 KiB
C++
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//===--------------------- Dispatch.cpp -------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file implements methods declared by class RegisterFile, DispatchUnit
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/// and RetireControlUnit.
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///
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//===----------------------------------------------------------------------===//
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#include "Dispatch.h"
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#include "Backend.h"
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#include "Scheduler.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "llvm-mca"
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namespace mca {
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void RegisterFile::addRegisterMapping(WriteState &WS) {
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unsigned RegID = WS.getRegisterID();
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assert(RegID && "Adding an invalid register definition?");
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RegisterMappings[RegID] = &WS;
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for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I)
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RegisterMappings[*I] = &WS;
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if (MaxUsedMappings == NumUsedMappings)
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MaxUsedMappings++;
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NumUsedMappings++;
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TotalMappingsCreated++;
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// If this is a partial update, then we are done.
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if (!WS.fullyUpdatesSuperRegs())
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return;
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for (MCSuperRegIterator I(RegID, &MRI); I.isValid(); ++I)
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RegisterMappings[*I] = &WS;
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}
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void RegisterFile::invalidateRegisterMapping(const WriteState &WS) {
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unsigned RegID = WS.getRegisterID();
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bool ShouldInvalidateSuperRegs = WS.fullyUpdatesSuperRegs();
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assert(RegID != 0 && "Invalidating an already invalid register?");
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assert(WS.getCyclesLeft() != -512 &&
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"Invalidating a write of unknown cycles!");
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assert(WS.getCyclesLeft() <= 0 && "Invalid cycles left for this write!");
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if (!RegisterMappings[RegID])
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return;
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assert(NumUsedMappings);
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NumUsedMappings--;
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if (RegisterMappings[RegID] == &WS)
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RegisterMappings[RegID] = nullptr;
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for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I)
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if (RegisterMappings[*I] == &WS)
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RegisterMappings[*I] = nullptr;
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if (!ShouldInvalidateSuperRegs)
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return;
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for (MCSuperRegIterator I(RegID, &MRI); I.isValid(); ++I)
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if (RegisterMappings[*I] == &WS)
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RegisterMappings[*I] = nullptr;
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}
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// Update the number of used mappings in the event of instruction retired.
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// This mehod delegates to the register file the task of invalidating
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// register mappings that were created for instruction IS.
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void DispatchUnit::invalidateRegisterMappings(const Instruction &IS) {
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for (const std::unique_ptr<WriteState> &WS : IS.getDefs()) {
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DEBUG(dbgs() << "[RAT] Invalidating mapping for: ");
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DEBUG(WS->dump());
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RAT->invalidateRegisterMapping(*WS.get());
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}
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}
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void RegisterFile::collectWrites(SmallVectorImpl<WriteState *> &Writes,
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unsigned RegID) const {
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assert(RegID && RegID < RegisterMappings.size());
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WriteState *WS = RegisterMappings[RegID];
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if (WS) {
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DEBUG(dbgs() << "Found a dependent use of RegID=" << RegID << '\n');
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Writes.push_back(WS);
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}
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// Handle potential partial register updates.
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for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I) {
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WS = RegisterMappings[*I];
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if (WS && std::find(Writes.begin(), Writes.end(), WS) == Writes.end()) {
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DEBUG(dbgs() << "Found a dependent use of subReg " << *I << " (part of "
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<< RegID << ")\n");
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Writes.push_back(WS);
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}
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}
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}
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bool RegisterFile::isAvailable(unsigned NumRegWrites) {
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if (!TotalMappings)
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return true;
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if (NumRegWrites > TotalMappings) {
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// The user specified a too small number of registers.
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// Artificially set the number of temporaries to NumRegWrites.
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errs() << "warning: not enough temporaries in the register file. "
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<< "The register file size has been automatically increased to "
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<< NumRegWrites << '\n';
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TotalMappings = NumRegWrites;
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}
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return NumRegWrites + NumUsedMappings <= TotalMappings;
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}
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#ifndef NDEBUG
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void RegisterFile::dump() const {
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for (unsigned I = 0, E = MRI.getNumRegs(); I < E; ++I)
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if (RegisterMappings[I]) {
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dbgs() << MRI.getName(I) << ", " << I << ", ";
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RegisterMappings[I]->dump();
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}
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dbgs() << "TotalMappingsCreated: " << TotalMappingsCreated
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<< ", MaxUsedMappings: " << MaxUsedMappings
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<< ", NumUsedMappings: " << NumUsedMappings << '\n';
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}
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#endif
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// Reserves a number of slots, and returns a new token.
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unsigned RetireControlUnit::reserveSlot(unsigned Index, unsigned NumMicroOps) {
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assert(isAvailable(NumMicroOps));
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unsigned NormalizedQuantity =
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std::min(NumMicroOps, static_cast<unsigned>(Queue.size()));
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// Zero latency instructions may have zero mOps. Artificially bump this
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// value to 1. Although zero latency instructions don't consume scheduler
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// resources, they still consume one slot in the retire queue.
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NormalizedQuantity = std::max(NormalizedQuantity, 1U);
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unsigned TokenID = NextAvailableSlotIdx;
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Queue[NextAvailableSlotIdx] = {Index, NormalizedQuantity, false};
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NextAvailableSlotIdx += NormalizedQuantity;
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NextAvailableSlotIdx %= Queue.size();
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AvailableSlots -= NormalizedQuantity;
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return TokenID;
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}
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void DispatchUnit::notifyInstructionDispatched(unsigned Index) {
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Owner->notifyInstructionDispatched(Index);
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}
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void DispatchUnit::notifyInstructionRetired(unsigned Index) {
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Owner->notifyInstructionRetired(Index);
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}
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void RetireControlUnit::cycleEvent() {
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if (isEmpty())
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return;
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unsigned NumRetired = 0;
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while (!isEmpty()) {
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if (MaxRetirePerCycle != 0 && NumRetired == MaxRetirePerCycle)
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break;
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RUToken &Current = Queue[CurrentInstructionSlotIdx];
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assert(Current.NumSlots && "Reserved zero slots?");
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if (!Current.Executed)
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break;
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Owner->notifyInstructionRetired(Current.Index);
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CurrentInstructionSlotIdx += Current.NumSlots;
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CurrentInstructionSlotIdx %= Queue.size();
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AvailableSlots += Current.NumSlots;
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NumRetired++;
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}
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}
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void RetireControlUnit::onInstructionExecuted(unsigned TokenID) {
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assert(Queue.size() > TokenID);
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assert(Queue[TokenID].Executed == false && Queue[TokenID].Index != ~0U);
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Queue[TokenID].Executed = true;
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}
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#ifndef NDEBUG
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void RetireControlUnit::dump() const {
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dbgs() << "Retire Unit: { Total Slots=" << Queue.size()
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<< ", Available Slots=" << AvailableSlots << " }\n";
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}
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#endif
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bool DispatchUnit::checkRAT(const InstrDesc &Desc) {
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unsigned NumWrites = Desc.Writes.size();
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if (RAT->isAvailable(NumWrites))
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return true;
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DispatchStalls[DS_RAT_REG_UNAVAILABLE]++;
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return false;
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}
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bool DispatchUnit::checkRCU(const InstrDesc &Desc) {
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unsigned NumMicroOps = Desc.NumMicroOps;
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if (RCU->isAvailable(NumMicroOps))
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return true;
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DispatchStalls[DS_RCU_TOKEN_UNAVAILABLE]++;
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return false;
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}
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bool DispatchUnit::checkScheduler(const InstrDesc &Desc) {
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// If this is a zero-latency instruction, then it bypasses
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// the scheduler.
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switch (SC->canBeDispatched(Desc)) {
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case Scheduler::HWS_AVAILABLE:
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return true;
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case Scheduler::HWS_QUEUE_UNAVAILABLE:
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DispatchStalls[DS_SQ_TOKEN_UNAVAILABLE]++;
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break;
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case Scheduler::HWS_LD_QUEUE_UNAVAILABLE:
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DispatchStalls[DS_LDQ_TOKEN_UNAVAILABLE]++;
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break;
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case Scheduler::HWS_ST_QUEUE_UNAVAILABLE:
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DispatchStalls[DS_STQ_TOKEN_UNAVAILABLE]++;
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break;
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case Scheduler::HWS_DISPATCH_GROUP_RESTRICTION:
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DispatchStalls[DS_DISPATCH_GROUP_RESTRICTION]++;
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}
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return false;
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}
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unsigned DispatchUnit::dispatch(unsigned IID, Instruction *NewInst) {
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assert(!CarryOver && "Cannot dispatch another instruction!");
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unsigned NumMicroOps = NewInst->getDesc().NumMicroOps;
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if (NumMicroOps > DispatchWidth) {
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assert(AvailableEntries == DispatchWidth);
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AvailableEntries = 0;
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CarryOver = NumMicroOps - DispatchWidth;
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} else {
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assert(AvailableEntries >= NumMicroOps);
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AvailableEntries -= NumMicroOps;
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}
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// Reserve slots in the RCU.
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unsigned RCUTokenID = RCU->reserveSlot(IID, NumMicroOps);
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Owner->notifyInstructionDispatched(IID);
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SC->scheduleInstruction(IID, NewInst);
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return RCUTokenID;
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}
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#ifndef NDEBUG
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void DispatchUnit::dump() const {
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RAT->dump();
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RCU->dump();
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unsigned DSRAT = DispatchStalls[DS_RAT_REG_UNAVAILABLE];
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unsigned DSRCU = DispatchStalls[DS_RCU_TOKEN_UNAVAILABLE];
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unsigned DSSCHEDQ = DispatchStalls[DS_SQ_TOKEN_UNAVAILABLE];
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unsigned DSLQ = DispatchStalls[DS_LDQ_TOKEN_UNAVAILABLE];
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unsigned DSSQ = DispatchStalls[DS_STQ_TOKEN_UNAVAILABLE];
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dbgs() << "STALLS --- RAT: " << DSRAT << ", RCU: " << DSRCU
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<< ", SCHED_QUEUE: " << DSSCHEDQ << ", LOAD_QUEUE: " << DSLQ
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<< ", STORE_QUEUE: " << DSSQ << '\n';
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}
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#endif
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} // namespace mca
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