RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 03:02:36 +01:00
Code Issues Projects Releases Wiki Activity
d30f6cb8e4
llvm-mirror/test/MC/RISCV/rv64zbs-valid.s

36 lines
1.4 KiB
ArmAsm
Raw Normal View History

[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92). It is implemented with each category of instruction as its own target feature, with the 'b' extension feature enabling all options. Since this extension is not yet ratified, all target features are prefixed with 'experimental-' to note their status. Differential Revision: https://reviews.llvm.org/D65649
2020-04-09 18:51:10 +02:00
# With B extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
[RISCV] Fix unused check prefixes in test/MC/RISCV/
2020-10-30 05:18:00 +01:00
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92). It is implemented with each category of instruction as its own target feature, with the 'b' extension feature enabling all options. Since this extension is not yet ratified, all target features are prefixed with 'experimental-' to note their status. Differential Revision: https://reviews.llvm.org/D65649
2020-04-09 18:51:10 +02:00
# With Bitmanip single bit extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbs -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbs < %s \
# RUN: | llvm-objdump --mattr=+experimental-zbs -d -r - \
[RISCV] Fix unused check prefixes in test/MC/RISCV/
2020-10-30 05:18:00 +01:00
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92). It is implemented with each category of instruction as its own target feature, with the 'b' extension feature enabling all options. Since this extension is not yet ratified, all target features are prefixed with 'experimental-' to note their status. Differential Revision: https://reviews.llvm.org/D65649
2020-04-09 18:51:10 +02:00
[RISCV] Rename Zbs instructions to start with just 'b' instead of 'sb' to match 0.93 bitmanip spec. Also renamed Zbe instructions to resolve name conflict even though that change is in the 0.94 draft. Reviewed By: asb, frasercrmck Differential Revision: https://reviews.llvm.org/D94653
2021-01-22 20:32:33 +01:00
# CHECK-ASM-AND-OBJ: bclrw t0, t1, t2
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92). It is implemented with each category of instruction as its own target feature, with the 'b' extension feature enabling all options. Since this extension is not yet ratified, all target features are prefixed with 'experimental-' to note their status. Differential Revision: https://reviews.llvm.org/D65649
2020-04-09 18:51:10 +02:00
# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x48]
[RISCV] Rename Zbs instructions to start with just 'b' instead of 'sb' to match 0.93 bitmanip spec. Also renamed Zbe instructions to resolve name conflict even though that change is in the 0.94 draft. Reviewed By: asb, frasercrmck Differential Revision: https://reviews.llvm.org/D94653
2021-01-22 20:32:33 +01:00
bclrw t0, t1, t2
# CHECK-ASM-AND-OBJ: bsetw t0, t1, t2
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92). It is implemented with each category of instruction as its own target feature, with the 'b' extension feature enabling all options. Since this extension is not yet ratified, all target features are prefixed with 'experimental-' to note their status. Differential Revision: https://reviews.llvm.org/D65649
2020-04-09 18:51:10 +02:00
# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x28]
[RISCV] Rename Zbs instructions to start with just 'b' instead of 'sb' to match 0.93 bitmanip spec. Also renamed Zbe instructions to resolve name conflict even though that change is in the 0.94 draft. Reviewed By: asb, frasercrmck Differential Revision: https://reviews.llvm.org/D94653
2021-01-22 20:32:33 +01:00
bsetw t0, t1, t2
# CHECK-ASM-AND-OBJ: binvw t0, t1, t2
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92). It is implemented with each category of instruction as its own target feature, with the 'b' extension feature enabling all options. Since this extension is not yet ratified, all target features are prefixed with 'experimental-' to note their status. Differential Revision: https://reviews.llvm.org/D65649
2020-04-09 18:51:10 +02:00
# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x68]
[RISCV] Rename Zbs instructions to start with just 'b' instead of 'sb' to match 0.93 bitmanip spec. Also renamed Zbe instructions to resolve name conflict even though that change is in the 0.94 draft. Reviewed By: asb, frasercrmck Differential Revision: https://reviews.llvm.org/D94653
2021-01-22 20:32:33 +01:00
binvw t0, t1, t2
# CHECK-ASM-AND-OBJ: bextw t0, t1, t2
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92). It is implemented with each category of instruction as its own target feature, with the 'b' extension feature enabling all options. Since this extension is not yet ratified, all target features are prefixed with 'experimental-' to note their status. Differential Revision: https://reviews.llvm.org/D65649
2020-04-09 18:51:10 +02:00
# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x48]
[RISCV] Rename Zbs instructions to start with just 'b' instead of 'sb' to match 0.93 bitmanip spec. Also renamed Zbe instructions to resolve name conflict even though that change is in the 0.94 draft. Reviewed By: asb, frasercrmck Differential Revision: https://reviews.llvm.org/D94653
2021-01-22 20:32:33 +01:00
bextw t0, t1, t2
# CHECK-ASM-AND-OBJ: bclriw t0, t1, 0
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92). It is implemented with each category of instruction as its own target feature, with the 'b' extension feature enabling all options. Since this extension is not yet ratified, all target features are prefixed with 'experimental-' to note their status. Differential Revision: https://reviews.llvm.org/D65649
2020-04-09 18:51:10 +02:00
# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x48]
[RISCV] Rename Zbs instructions to start with just 'b' instead of 'sb' to match 0.93 bitmanip spec. Also renamed Zbe instructions to resolve name conflict even though that change is in the 0.94 draft. Reviewed By: asb, frasercrmck Differential Revision: https://reviews.llvm.org/D94653
2021-01-22 20:32:33 +01:00
bclriw t0, t1, 0
# CHECK-ASM-AND-OBJ: bsetiw t0, t1, 0
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92). It is implemented with each category of instruction as its own target feature, with the 'b' extension feature enabling all options. Since this extension is not yet ratified, all target features are prefixed with 'experimental-' to note their status. Differential Revision: https://reviews.llvm.org/D65649
2020-04-09 18:51:10 +02:00
# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x28]
[RISCV] Rename Zbs instructions to start with just 'b' instead of 'sb' to match 0.93 bitmanip spec. Also renamed Zbe instructions to resolve name conflict even though that change is in the 0.94 draft. Reviewed By: asb, frasercrmck Differential Revision: https://reviews.llvm.org/D94653
2021-01-22 20:32:33 +01:00
bsetiw t0, t1, 0
# CHECK-ASM-AND-OBJ: binviw t0, t1, 0
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92). It is implemented with each category of instruction as its own target feature, with the 'b' extension feature enabling all options. Since this extension is not yet ratified, all target features are prefixed with 'experimental-' to note their status. Differential Revision: https://reviews.llvm.org/D65649
2020-04-09 18:51:10 +02:00
# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x68]
[RISCV] Rename Zbs instructions to start with just 'b' instead of 'sb' to match 0.93 bitmanip spec. Also renamed Zbe instructions to resolve name conflict even though that change is in the 0.94 draft. Reviewed By: asb, frasercrmck Differential Revision: https://reviews.llvm.org/D94653
2021-01-22 20:32:33 +01:00
binviw t0, t1, 0
Reference in New Issue Copy Permalink