llvm-mirror/test/CodeGen/X86/2011-10-11-srl.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=-sse4.1

target triple = "x86_64-unknown-linux-gnu"

define void @m387(<2 x i8>* %p, <2 x i16>* %q) {
  %t = load <2 x i8>, <2 x i8>* %p
  %r = sext <2 x i8> %t to <2 x i16>
  store <2 x i16> %r, <2 x i16>* %q
  ret void
}
Replace more uses of sse41 with sse4.1. llc using the host cpu features and waning on unknown features is probably not a good thing :-( llvm-svn: 189144 2013-08-23 22:39:19 +02:00			`; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=-sse4.1`
Add support for legalization of vector SHL/SRA/SRL instructions llvm-svn: 141667 2011-10-11 16:36:35 +02:00
			`target triple = "x86_64-unknown-linux-gnu"`

			`define void @m387(<2 x i8>* %p, <2 x i16>* %q) {`
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=\|:\|^)\sload (?:atomic )?(?:volatile )?(.?))(\| addrspace\(\d+\) )\($\| (?:%\|@\|null\|undef\|blockaddress\|getelementptr\|addrspacecast\|bitcast\|inttoptr\|\[\[[a-zA-Z]\|\{\{).$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794 2015-02-27 22:17:42 +01:00			`%t = load <2 x i8>, <2 x i8>* %p`
Add support for legalization of vector SHL/SRA/SRL instructions llvm-svn: 141667 2011-10-11 16:36:35 +02:00			`%r = sext <2 x i8> %t to <2 x i16>`
			`store <2 x i16> %r, <2 x i16>* %q`
			`ret void`
			`}`