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llvm-mirror/test/MC/AVR/inst-xch.s

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[AVR] Add all of the machine code test suite Summary: This adds all of the AVR machine code tests. Reviewers: arsenm, kparzysz Subscribers: wdng, japaric Differential Revision: https://reviews.llvm.org/D26387 llvm-svn: 286417
2016-11-10 00:46:25 +01:00
; RUN: llvm-mc -triple avr -mattr=rmw -show-encoding < %s | FileCheck %s
[AVR] Disassemble instructions with fixed Z operand Some instructions have a fixed Z register and don't have an explicit register operand. This can be worked around by simply printing the operand directly if the particular register class is detected. The LPM and ELPM instructions also needed a custom decoder, which is also included in this patch. Differential Revision: https://reviews.llvm.org/D82088
2020-06-18 14:41:17 +02:00
; RUN: llvm-mc -filetype=obj -triple avr -mattr=rmw < %s | llvm-objdump -d --mattr=rmw - | FileCheck -check-prefix=CHECK-INST %s
[AVR] Add all of the machine code test suite Summary: This adds all of the AVR machine code tests. Reviewers: arsenm, kparzysz Subscribers: wdng, japaric Differential Revision: https://reviews.llvm.org/D26387 llvm-svn: 286417
2016-11-10 00:46:25 +01:00
foo:
xch Z, r13
xch Z, r0
xch Z, r31
xch Z, r3
; CHECK: xch Z, r13 ; encoding: [0xd4,0x92]
; CHECK: xch Z, r0 ; encoding: [0x04,0x92]
; CHECK: xch Z, r31 ; encoding: [0xf4,0x93]
; CHECK: xch Z, r3 ; encoding: [0x34,0x92]
[AVR] Disassemble instructions with fixed Z operand Some instructions have a fixed Z register and don't have an explicit register operand. This can be worked around by simply printing the operand directly if the particular register class is detected. The LPM and ELPM instructions also needed a custom decoder, which is also included in this patch. Differential Revision: https://reviews.llvm.org/D82088
2020-06-18 14:41:17 +02:00
; CHECK-INST: xch Z, r13
; CHECK-INST: xch Z, r0
; CHECK-INST: xch Z, r31
; CHECK-INST: xch Z, r3
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