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llvm-mirror/test/CodeGen/SystemZ/cond-move-02.ll

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[SystemZ] Improve use of conditional instructions This patch moves formation of LOC-type instructions from (late) IfConversion to the early if-conversion pass, and in some cases additionally creates them directly from select instructions during DAG instruction selection. To make early if-conversion work, the patch implements the canInsertSelect / insertSelect callbacks. It also implements the commuteInstructionImpl and FoldImmediate callbacks to enable generation of the full range of LOC instructions. Finally, the patch adds support for all instructions of the load-store-on-condition-2 facility, which allows using LOC instructions also for high registers. Due to the use of the GRX32 register class to enable high registers, we now also have to handle the cases where there are still no single hardware instructions (conditional move from a low register to a high register or vice versa). These are converted back to a branch sequence after register allocation. Since the expandRAPseudos callback is not allowed to create new basic blocks, this requires a simple new pass, modelled after the ARM/AArch64 ExpandPseudos pass. Overall, this patch causes significantly more LOC-type instructions to be used, and results in a measurable performance improvement. llvm-svn: 288028
2016-11-28 14:34:08 +01:00
; Test LOCHI and LOCGHI.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -verify-machineinstrs | FileCheck %s
define i32 @f1(i32 %x) {
; CHECK-LABEL: f1:
; CHECK: chi %r2, 0
[SystemZ] Do not use glue to represent condition code dependencies Currently, an instruction setting the condition code is linked to the instruction using the condition code via a "glue" link in the SelectionDAG. This has a number of drawbacks; in particular, it means the same CC cannot be used by multiple users. It also makes it more difficult to efficiently implement SADDO et. al. This patch changes the back-end to represent CC dependencies as normal values during SelectionDAG matching, along the lines of how this is handled in the X86 back-end already. In addition to the core mechanics of updating all relevant patterns, this requires a number of additional changes: - We now need to be able to spill/restore a CC value into a GPR if necessary. This means providing a copyPhysReg implementation for moves involving CC, and defining getCrossCopyRegClass. - Since we still prefer to avoid such spills, we provide an override for IsProfitableToFold to avoid creating a merged LOAD / ICMP if this would result in multiple users of the CC. - combineCCMask no longer requires a single CC user, and no longer need to be careful about preventing invalid glue/chain cycles. - emitSelect needs to be more careful in marking CC live-in to the basic block it generates. Also, we can now optimize the case of multiple subsequent selects with the same condition just like X86 does. llvm-svn: 331202
2018-04-30 19:52:32 +02:00
; CHECK: lhi %r2, 0
; CHECK: lochilh %r2, 42
[SystemZ] Improve use of conditional instructions This patch moves formation of LOC-type instructions from (late) IfConversion to the early if-conversion pass, and in some cases additionally creates them directly from select instructions during DAG instruction selection. To make early if-conversion work, the patch implements the canInsertSelect / insertSelect callbacks. It also implements the commuteInstructionImpl and FoldImmediate callbacks to enable generation of the full range of LOC instructions. Finally, the patch adds support for all instructions of the load-store-on-condition-2 facility, which allows using LOC instructions also for high registers. Due to the use of the GRX32 register class to enable high registers, we now also have to handle the cases where there are still no single hardware instructions (conditional move from a low register to a high register or vice versa). These are converted back to a branch sequence after register allocation. Since the expandRAPseudos callback is not allowed to create new basic blocks, this requires a simple new pass, modelled after the ARM/AArch64 ExpandPseudos pass. Overall, this patch causes significantly more LOC-type instructions to be used, and results in a measurable performance improvement. llvm-svn: 288028
2016-11-28 14:34:08 +01:00
; CHECK: br %r14
%cond = icmp ne i32 %x, 0
%res = select i1 %cond, i32 42, i32 0
ret i32 %res
}
define i32 @f2(i32 %x, i32 %y) {
; CHECK-LABEL: f2:
; CHECK: chi %r2, 0
; CHECK: lochilh %r3, 42
; CHECK: br %r14
%cond = icmp ne i32 %x, 0
%res = select i1 %cond, i32 42, i32 %y
ret i32 %res
}
define i32 @f3(i32 %x, i32 %y) {
; CHECK-LABEL: f3:
; CHECK: chi %r2, 0
; CHECK: lochie %r3, 42
; CHECK: br %r14
%cond = icmp ne i32 %x, 0
%res = select i1 %cond, i32 %y, i32 42
ret i32 %res
}
define i64 @f4(i64 %x) {
; CHECK-LABEL: f4:
; CHECK: cghi %r2, 0
[SystemZ] Do not use glue to represent condition code dependencies Currently, an instruction setting the condition code is linked to the instruction using the condition code via a "glue" link in the SelectionDAG. This has a number of drawbacks; in particular, it means the same CC cannot be used by multiple users. It also makes it more difficult to efficiently implement SADDO et. al. This patch changes the back-end to represent CC dependencies as normal values during SelectionDAG matching, along the lines of how this is handled in the X86 back-end already. In addition to the core mechanics of updating all relevant patterns, this requires a number of additional changes: - We now need to be able to spill/restore a CC value into a GPR if necessary. This means providing a copyPhysReg implementation for moves involving CC, and defining getCrossCopyRegClass. - Since we still prefer to avoid such spills, we provide an override for IsProfitableToFold to avoid creating a merged LOAD / ICMP if this would result in multiple users of the CC. - combineCCMask no longer requires a single CC user, and no longer need to be careful about preventing invalid glue/chain cycles. - emitSelect needs to be more careful in marking CC live-in to the basic block it generates. Also, we can now optimize the case of multiple subsequent selects with the same condition just like X86 does. llvm-svn: 331202
2018-04-30 19:52:32 +02:00
; CHECK: lghi %r2, 0
; CHECK: locghilh %r2, 42
[SystemZ] Improve use of conditional instructions This patch moves formation of LOC-type instructions from (late) IfConversion to the early if-conversion pass, and in some cases additionally creates them directly from select instructions during DAG instruction selection. To make early if-conversion work, the patch implements the canInsertSelect / insertSelect callbacks. It also implements the commuteInstructionImpl and FoldImmediate callbacks to enable generation of the full range of LOC instructions. Finally, the patch adds support for all instructions of the load-store-on-condition-2 facility, which allows using LOC instructions also for high registers. Due to the use of the GRX32 register class to enable high registers, we now also have to handle the cases where there are still no single hardware instructions (conditional move from a low register to a high register or vice versa). These are converted back to a branch sequence after register allocation. Since the expandRAPseudos callback is not allowed to create new basic blocks, this requires a simple new pass, modelled after the ARM/AArch64 ExpandPseudos pass. Overall, this patch causes significantly more LOC-type instructions to be used, and results in a measurable performance improvement. llvm-svn: 288028
2016-11-28 14:34:08 +01:00
; CHECK: br %r14
%cond = icmp ne i64 %x, 0
%res = select i1 %cond, i64 42, i64 0
ret i64 %res
}
define i64 @f5(i64 %x, i64 %y) {
; CHECK-LABEL: f5:
; CHECK: cghi %r2, 0
; CHECK: locghilh %r3, 42
; CHECK: br %r14
%cond = icmp ne i64 %x, 0
%res = select i1 %cond, i64 42, i64 %y
ret i64 %res
}
define i64 @f6(i64 %x, i64 %y) {
; CHECK-LABEL: f6:
; CHECK: cghi %r2, 0
; CHECK: locghie %r3, 42
; CHECK: br %r14
%cond = icmp ne i64 %x, 0
%res = select i1 %cond, i64 %y, i64 42
ret i64 %res
}
; Check that we also get LOCHI as a result of early if-conversion.
define i32 @f7(i32 %x, i32 %y) {
; CHECK-LABEL: f7:
; CHECK: chi %r2, 0
; CHECK: lochie %r3, 42
; CHECK: br %r14
entry:
%cond = icmp ne i32 %x, 0
br i1 %cond, label %if.then, label %return
if.then:
br label %return
return:
%res = phi i32 [ %y, %if.then ], [ 42, %entry ]
ret i32 %res
}
; ... and the same for LOCGHI.
define i64 @f8(i64 %x, i64 %y) {
; CHECK-LABEL: f8:
; CHECK: cghi %r2, 0
; CHECK: locghie %r3, 42
; CHECK: br %r14
entry:
%cond = icmp ne i64 %x, 0
br i1 %cond, label %if.then, label %return
if.then:
br label %return
return:
%res = phi i64 [ %y, %if.then ], [ 42, %entry ]
ret i64 %res
}
; Check that inverting the condition works as well.
define i32 @f9(i32 %x, i32 %y) {
; CHECK-LABEL: f9:
; CHECK: chi %r2, 0
; CHECK: lochilh %r3, 42
; CHECK: br %r14
entry:
%cond = icmp ne i32 %x, 0
br i1 %cond, label %if.then, label %return
if.then:
br label %return
return:
%res = phi i32 [ 42, %if.then ], [ %y, %entry ]
ret i32 %res
}
; ... and the same for LOCGHI.
define i64 @f10(i64 %x, i64 %y) {
; CHECK-LABEL: f10:
; CHECK: cghi %r2, 0
; CHECK: locghilh %r3, 42
; CHECK: br %r14
entry:
%cond = icmp ne i64 %x, 0
br i1 %cond, label %if.then, label %return
if.then:
br label %return
return:
%res = phi i64 [ 42, %if.then ], [ %y, %entry ]
ret i64 %res
}
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