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llvm-mirror/test/TableGen/AsmPredicateCombiningRISCV.td

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[TableGen] Support combining AssemblerPredicates with ORs For context, the proposed RISC-V bit manipulation extension has a subset of instructions which require one of two SubtargetFeatures to be enabled, 'zbb' or 'zbp', and there is no defined feature which both of these can imply to use as a constraint either (see comments in D65649). AssemblerPredicates allow multiple SubtargetFeatures to be declared in the "AssemblerCondString" field, separated by commas, and this means that the two features must both be enabled. There is no equivalent to say that _either_ feature X or feature Y must be enabled, short of creating a dummy SubtargetFeature for this purpose and having features X and Y imply the new feature. To solve the case where X or Y is needed without adding a new feature, and to better match a typical TableGen style, this replaces the existing "AssemblerCondString" with a dag "AssemblerCondDag" which represents the same information. Two operators are defined for use with AssemblerCondDag, "all_of", which matches the current behaviour, and "any_of", which adds the new proposed ORing features functionality. This was originally proposed in the RFC at http://lists.llvm.org/pipermail/llvm-dev/2020-February/139138.html Changes to all current backends are mechanical to support the replaced functionality, and are NFCI. At this stage, it is illegal to combine features with ands and ors in a single AssemblerCondDag. I suspect this case is sufficiently rare that adding more complex changes to support it are unnecessary. Differential Revision: https://reviews.llvm.org/D74338
2020-03-13 18:13:51 +01:00
// RUN: llvm-tblgen -gen-compress-inst-emitter -I %p/../../include %s | \
// RUN: FileCheck --check-prefix=COMPRESS %s
// Check that combining conditions in AssemblerPredicate generates the correct
// output when using both the (all_of) AND operator, and the (any_of) OR
// operator in the RISC-V specific instruction compressor.
include "llvm/Target/Target.td"
def archInstrInfo : InstrInfo { }
def archAsmWriter : AsmWriter {
int PassSubtarget = 1;
}
def arch : Target {
let InstructionSet = archInstrInfo;
let AssemblyWriters = [archAsmWriter];
}
let Namespace = "arch" in {
def R0 : Register<"r0">;
}
def Regs : RegisterClass<"Regs", [i32], 32, (add R0)>;
class RVInst<int Opc, list<Predicate> Preds> : Instruction {
let Size = 4;
let OutOperandList = (outs);
let InOperandList = (ins Regs:$r);
field bits<32> Inst;
let Inst = Opc;
let AsmString = NAME # " $r";
field bits<32> SoftFail = 0;
let Predicates = Preds;
}
class RVInst16<int Opc, list<Predicate> Preds> : Instruction {
let Size = 2;
let OutOperandList = (outs);
let InOperandList = (ins Regs:$r);
field bits<16> Inst;
let Inst = Opc;
let AsmString = NAME # " $r";
field bits<16> SoftFail = 0;
let Predicates = Preds;
}
def AsmCond1 : SubtargetFeature<"cond1", "cond1", "true", "">;
def AsmCond2a: SubtargetFeature<"cond2a", "cond2a", "true", "">;
def AsmCond2b: SubtargetFeature<"cond2b", "cond2b", "true", "">;
def AsmCond3a: SubtargetFeature<"cond3a", "cond3a", "true", "">;
def AsmCond3b: SubtargetFeature<"cond3b", "cond3b", "true", "">;
def AsmPred1 : Predicate<"Pred1">, AssemblerPredicate<(all_of AsmCond1)>;
def AsmPred2 : Predicate<"Pred2">, AssemblerPredicate<(all_of AsmCond2a, AsmCond2b)>;
def AsmPred3 : Predicate<"Pred3">, AssemblerPredicate<(any_of AsmCond3a, AsmCond3b)>;
def BigInst : RVInst<1, [AsmPred1]>;
class CompressPat<dag input, dag output, list<Predicate> predicates> {
dag Input = input;
dag Output = output;
list<Predicate> Predicates = predicates;
[RISCV] Add way to mark CompressPats that should only be used for compressing. There can be muliple patterns that map to the same compressed instruction. Reversing those leads to multiple ways to uncompress an instruction, but its not easily controllable which one will be chosen by the tablegen backend. This patch adds a flag to mark patterns that should only be used for compressing. This allows us to leave one canonical pattern for uncompressing. The obvious benefit of this is getting c.mv to uncompress to the addi patern that is aliased to the mv pseudoinstruction. For the add/and/or/xor/li patterns it just removes some unreachable code from the generated code. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D94894
2021-01-20 18:19:57 +01:00
bit isCompressOnly = false;
[TableGen] Support combining AssemblerPredicates with ORs For context, the proposed RISC-V bit manipulation extension has a subset of instructions which require one of two SubtargetFeatures to be enabled, 'zbb' or 'zbp', and there is no defined feature which both of these can imply to use as a constraint either (see comments in D65649). AssemblerPredicates allow multiple SubtargetFeatures to be declared in the "AssemblerCondString" field, separated by commas, and this means that the two features must both be enabled. There is no equivalent to say that _either_ feature X or feature Y must be enabled, short of creating a dummy SubtargetFeature for this purpose and having features X and Y imply the new feature. To solve the case where X or Y is needed without adding a new feature, and to better match a typical TableGen style, this replaces the existing "AssemblerCondString" with a dag "AssemblerCondDag" which represents the same information. Two operators are defined for use with AssemblerCondDag, "all_of", which matches the current behaviour, and "any_of", which adds the new proposed ORing features functionality. This was originally proposed in the RFC at http://lists.llvm.org/pipermail/llvm-dev/2020-February/139138.html Changes to all current backends are mechanical to support the replaced functionality, and are NFCI. At this stage, it is illegal to combine features with ands and ors in a single AssemblerCondDag. I suspect this case is sufficiently rare that adding more complex changes to support it are unnecessary. Differential Revision: https://reviews.llvm.org/D74338
2020-03-13 18:13:51 +01:00
}
// COMPRESS-LABEL: static bool compressInst
// COMPRESS: case arch::BigInst
def SmallInst1 : RVInst16<1, []>;
def : CompressPat<(BigInst Regs:$r), (SmallInst1 Regs:$r), [AsmPred1]>;
// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] &&
// COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
// COMPRESS-NEXT: // SmallInst1 $r
def SmallInst2 : RVInst16<2, []>;
def : CompressPat<(BigInst Regs:$r), (SmallInst2 Regs:$r), [AsmPred2]>;
// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond2a] &&
// COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2b] &&
// COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
// COMPRESS-NEXT: // SmallInst2 $r
def SmallInst3 : RVInst16<2, []>;
def : CompressPat<(BigInst Regs:$r), (SmallInst3 Regs:$r), [AsmPred3]>;
// COMPRESS: if ((STI.getFeatureBits()[arch::AsmCond3a] || STI.getFeatureBits()[arch::AsmCond3b]) &&
// COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
// COMPRESS-NEXT: // SmallInst3 $r
def SmallInst4 : RVInst16<2, []>;
def : CompressPat<(BigInst Regs:$r), (SmallInst4 Regs:$r), [AsmPred1, AsmPred2]>;
// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] &&
// COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2a] &&
// COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2b] &&
// COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
// COMPRESS-NEXT: // SmallInst4 $r
def SmallInst5 : RVInst16<2, []>;
def : CompressPat<(BigInst Regs:$r), (SmallInst5 Regs:$r), [AsmPred1, AsmPred3]>;
// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] &&
// COMPRESS-NEXT: (STI.getFeatureBits()[arch::AsmCond3a] || STI.getFeatureBits()[arch::AsmCond3b]) &&
// COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
// COMPRESS-NEXT: // SmallInst5 $r
// COMPRESS-LABEL: static bool uncompressInst
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