Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
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//===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
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//
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2019-01-19 09:50:56 +01:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file declares the targeting of the InstructionSelector class for
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/// AMDGPU.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
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2017-03-27 16:04:01 +02:00
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#include "AMDGPU.h"
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2018-06-25 18:17:48 +02:00
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#include "AMDGPUArgumentUsageInfo.h"
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/SmallVector.h"
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2019-07-01 18:06:02 +02:00
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#include "llvm/CodeGen/Register.h"
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2017-06-06 13:49:48 +02:00
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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2019-07-01 15:34:26 +02:00
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#include "llvm/IR/InstrTypes.h"
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
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AMDGPU/GlobalISel: Enable TableGen'd instruction selector
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45994
llvm-svn: 332039
2018-05-10 22:53:06 +02:00
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namespace {
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#define GET_GLOBALISEL_PREDICATE_BITSET
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2018-07-11 22:59:01 +02:00
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#define AMDGPUSubtarget GCNSubtarget
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AMDGPU/GlobalISel: Enable TableGen'd instruction selector
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45994
llvm-svn: 332039
2018-05-10 22:53:06 +02:00
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#include "AMDGPUGenGlobalISel.inc"
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#undef GET_GLOBALISEL_PREDICATE_BITSET
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2018-07-11 22:59:01 +02:00
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#undef AMDGPUSubtarget
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AMDGPU/GlobalISel: Enable TableGen'd instruction selector
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45994
llvm-svn: 332039
2018-05-10 22:53:06 +02:00
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}
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Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
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namespace llvm {
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2020-02-08 05:37:54 +01:00
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namespace AMDGPU {
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struct ImageDimIntrinsicInfo;
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}
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Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
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class AMDGPUInstrInfo;
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class AMDGPURegisterBankInfo;
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2018-07-11 22:59:01 +02:00
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class GCNSubtarget;
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Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
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class MachineInstr;
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2019-09-19 18:26:14 +02:00
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class MachineIRBuilder;
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
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class MachineOperand;
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class MachineRegisterInfo;
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AMDGPU/GlobalISel: Replace handling of boolean values
This solves selection failures with generated selection patterns,
which would fail due to inferring the SGPR reg bank for virtual
registers with a set register class instead of VCC bank. Use
instruction selection would constrain the virtual register to a
specific class, so when the def was selected later the bank no longer
was set to VCC.
Remove the SCC reg bank. SCC isn't directly addressable, so it
requires copying from SCC to an allocatable 32-bit register during
selection, so these might as well be treated as 32-bit SGPR values.
Now any scalar boolean value that will produce an outupt in SCC should
be widened during RegBankSelect to s32. Any s1 value should be a
vector boolean during selection. This makes the vcc register bank
unambiguous with a normal SGPR during selection.
Summary of how this should now work:
- G_TRUNC is always a no-op, and never should use a vcc bank result.
- SALU boolean operations should be promoted to s32 in RegBankSelect
apply mapping
- An s1 value means vcc bank at selection. The exception is for
legalization artifacts that use s1, which are never VCC. All other
contexts should infer the VCC register classes for s1 typed
registers. The LLT for the register is now needed to infer the
correct register class. Extensions with vcc sources should be
legalized to a select of constants during RegBankSelect.
- Copy from non-vcc to vcc ensures high bits of the input value are
cleared during selection.
- SALU boolean inputs should ensure the inputs are 0/1. This includes
select, conditional branches, and carry-ins.
There are a few somewhat dirty details. One is that G_TRUNC/G_*EXT
selection ignores the usual register-bank from register class
functions, and can't handle truncates with VCC result banks. I think
this is OK, since the artifacts are specially treated anyway. This
does require some care to avoid producing cases with vcc. There will
also be no 100% reliable way to verify this rule is followed in
selection in case of register classes, and violations manifests
themselves as invalid copy instructions much later.
Standard phi handling also only considers the bank of the result
register, and doesn't insert copies to make the source banks
match. This doesn't work for vcc, so we have to manually correct phi
inputs in this case. We should add a verifier check to make sure there
are no phis with mixed vcc and non-vcc register bank inputs.
There's also some duplication with the LegalizerHelper, and some code
which should live in the helper. I don't see a good way to share
special knowledge about what types to use for intermediate operations
depending on the bank for example. Using the helper to replace
extensions with selects also seems somewhat awkward to me.
Another issue is there are some contexts calling
getRegBankFromRegClass that apparently don't have the LLT type for the
register, but I haven't yet run into a real issue from this.
This also introduces new unnecessary instructions in most cases, since
we don't yet try to optimize out the zext when the source is known to
come from a compare.
2019-11-02 17:30:59 +01:00
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class RegisterBank;
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
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class SIInstrInfo;
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2018-06-25 18:17:48 +02:00
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class SIMachineFunctionInfo;
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
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class SIRegisterInfo;
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2020-07-26 16:52:51 +02:00
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class AMDGPUInstructionSelector final : public InstructionSelector {
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2019-09-28 05:41:13 +02:00
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private:
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MachineRegisterInfo *MRI;
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2020-09-14 10:39:25 +02:00
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const GCNSubtarget *Subtarget;
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2019-09-28 05:41:13 +02:00
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Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
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public:
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2018-07-11 22:59:01 +02:00
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AMDGPUInstructionSelector(const GCNSubtarget &STI,
|
AMDGPU/GlobalISel: Enable TableGen'd instruction selector
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45994
llvm-svn: 332039
2018-05-10 22:53:06 +02:00
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const AMDGPURegisterBankInfo &RBI,
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const AMDGPUTargetMachine &TM);
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
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2019-08-13 08:26:59 +02:00
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bool select(MachineInstr &I) override;
|
AMDGPU/GlobalISel: Enable TableGen'd instruction selector
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45994
llvm-svn: 332039
2018-05-10 22:53:06 +02:00
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static const char *getName();
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[globalisel][tablegen] Generate rule coverage and use it to identify untested rules
Summary:
This patch adds a LLVM_ENABLE_GISEL_COV which, like LLVM_ENABLE_DAGISEL_COV,
causes TableGen to instrument the generated table to collect rule coverage
information. However, LLVM_ENABLE_GISEL_COV goes a bit further than
LLVM_ENABLE_DAGISEL_COV. The information is written to files
(${CMAKE_BINARY_DIR}/gisel-coverage-* by default). These files can then be
concatenated into ${LLVM_GISEL_COV_PREFIX}-all after which TableGen will
read this information and use it to emit warnings about untested rules.
This technique could also be used by SelectionDAG and can be further
extended to detect hot rules and give them priority over colder rules.
Usage:
* Enable LLVM_ENABLE_GISEL_COV in CMake
* Build the compiler and run some tests
* cat gisel-coverage-[0-9]* > gisel-coverage-all
* Delete lib/Target/*/*GenGlobalISel.inc*
* Build the compiler
Known issues:
* ${LLVM_GISEL_COV_PREFIX}-all must be generated as a manual
step due to a lack of a portable 'cat' command. It should be the
concatenation of all ${LLVM_GISEL_COV_PREFIX}-[0-9]* files.
* There's no mechanism to discard coverage information when the ruleset
changes
Depends on D39742
Reviewers: ab, qcolombet, t.p.northover, aditya_nandakumar, rovka
Reviewed By: rovka
Subscribers: vsk, arsenm, nhaehnle, mgorny, kristof.beyls, javed.absar, igorb, llvm-commits
Differential Revision: https://reviews.llvm.org/D39747
llvm-svn: 318356
2017-11-16 01:46:35 +01:00
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2019-09-28 05:41:13 +02:00
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void setupMF(MachineFunction &MF, GISelKnownBits &KB,
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CodeGenCoverage &CoverageInfo) override;
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|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
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private:
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struct GEPInfo {
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const MachineInstr &GEP;
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SmallVector<unsigned, 2> SgprParts;
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SmallVector<unsigned, 2> VgprParts;
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int64_t Imm;
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GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
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};
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AMDGPU/GlobalISel: Move SMRD selection logic to TableGen
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: volkan, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D52922
llvm-svn: 354516
2019-02-20 22:02:37 +01:00
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bool isInstrUniform(const MachineInstr &MI) const;
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2019-07-01 18:06:02 +02:00
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bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
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AMDGPU/GlobalISel: Replace handling of boolean values
This solves selection failures with generated selection patterns,
which would fail due to inferring the SGPR reg bank for virtual
registers with a set register class instead of VCC bank. Use
instruction selection would constrain the virtual register to a
specific class, so when the def was selected later the bank no longer
was set to VCC.
Remove the SCC reg bank. SCC isn't directly addressable, so it
requires copying from SCC to an allocatable 32-bit register during
selection, so these might as well be treated as 32-bit SGPR values.
Now any scalar boolean value that will produce an outupt in SCC should
be widened during RegBankSelect to s32. Any s1 value should be a
vector boolean during selection. This makes the vcc register bank
unambiguous with a normal SGPR during selection.
Summary of how this should now work:
- G_TRUNC is always a no-op, and never should use a vcc bank result.
- SALU boolean operations should be promoted to s32 in RegBankSelect
apply mapping
- An s1 value means vcc bank at selection. The exception is for
legalization artifacts that use s1, which are never VCC. All other
contexts should infer the VCC register classes for s1 typed
registers. The LLT for the register is now needed to infer the
correct register class. Extensions with vcc sources should be
legalized to a select of constants during RegBankSelect.
- Copy from non-vcc to vcc ensures high bits of the input value are
cleared during selection.
- SALU boolean inputs should ensure the inputs are 0/1. This includes
select, conditional branches, and carry-ins.
There are a few somewhat dirty details. One is that G_TRUNC/G_*EXT
selection ignores the usual register-bank from register class
functions, and can't handle truncates with VCC result banks. I think
this is OK, since the artifacts are specially treated anyway. This
does require some care to avoid producing cases with vcc. There will
also be no 100% reliable way to verify this rule is followed in
selection in case of register classes, and violations manifests
themselves as invalid copy instructions much later.
Standard phi handling also only considers the bank of the result
register, and doesn't insert copies to make the source banks
match. This doesn't work for vcc, so we have to manually correct phi
inputs in this case. We should add a verifier check to make sure there
are no phis with mixed vcc and non-vcc register bank inputs.
There's also some duplication with the LegalizerHelper, and some code
which should live in the helper. I don't see a good way to share
special knowledge about what types to use for intermediate operations
depending on the bank for example. Using the helper to replace
extensions with selects also seems somewhat awkward to me.
Another issue is there are some contexts calling
getRegBankFromRegClass that apparently don't have the LLT type for the
register, but I haven't yet run into a real issue from this.
This also introduces new unnecessary instructions in most cases, since
we don't yet try to optimize out the zext when the source is known to
come from a compare.
2019-11-02 17:30:59 +01:00
|
|
|
const RegisterBank *getArtifactRegBank(
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Register Reg, const MachineRegisterInfo &MRI,
|
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const TargetRegisterInfo &TRI) const;
|
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|
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|
AMDGPU/GlobalISel: Enable TableGen'd instruction selector
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45994
llvm-svn: 332039
2018-05-10 22:53:06 +02:00
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/// tblgen-erated 'select' implementation.
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bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
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2019-07-01 18:34:48 +02:00
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MachineOperand getSubOperand64(MachineOperand &MO,
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const TargetRegisterClass &SubRC,
|
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unsigned SubIdx) const;
|
2020-01-17 06:22:23 +01:00
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bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
|
2018-05-10 23:20:10 +02:00
|
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bool selectCOPY(MachineInstr &I) const;
|
2019-07-01 18:32:47 +02:00
|
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bool selectPHI(MachineInstr &I) const;
|
2019-06-24 20:02:18 +02:00
|
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|
bool selectG_TRUNC(MachineInstr &I) const;
|
2019-06-25 15:18:11 +02:00
|
|
|
bool selectG_SZA_EXT(MachineInstr &I) const;
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
|
|
|
bool selectG_CONSTANT(MachineInstr &I) const;
|
2020-01-26 01:34:22 +01:00
|
|
|
bool selectG_FNEG(MachineInstr &I) const;
|
2020-04-07 17:33:26 +02:00
|
|
|
bool selectG_FABS(MachineInstr &I) const;
|
2019-07-15 21:50:07 +02:00
|
|
|
bool selectG_AND_OR_XOR(MachineInstr &I) const;
|
2019-07-09 16:05:11 +02:00
|
|
|
bool selectG_ADD_SUB(MachineInstr &I) const;
|
2019-12-25 15:06:05 +01:00
|
|
|
bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
|
2019-03-01 00:37:48 +01:00
|
|
|
bool selectG_EXTRACT(MachineInstr &I) const;
|
2019-07-09 16:02:20 +02:00
|
|
|
bool selectG_MERGE_VALUES(MachineInstr &I) const;
|
2019-07-09 16:02:26 +02:00
|
|
|
bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
|
2020-02-15 23:14:17 +01:00
|
|
|
bool selectG_BUILD_VECTOR_TRUNC(MachineInstr &I) const;
|
[globalisel] Rename G_GEP to G_PTR_ADD
Summary:
G_GEP is rather poorly named. It's a simple pointer+scalar addition and
doesn't support any of the complexities of getelementptr. I therefore
propose that we rename it. There's a G_PTR_MASK so let's follow that
convention and go with G_PTR_ADD
Reviewers: volkan, aditya_nandakumar, bogner, rovka, arsenm
Subscribers: sdardis, jvesely, wdng, nhaehnle, hiraditya, jrtc27, atanasyan, arphaman, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69734
2019-11-01 21:18:00 +01:00
|
|
|
bool selectG_PTR_ADD(MachineInstr &I) const;
|
2018-06-22 01:38:20 +02:00
|
|
|
bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
|
AMDGPU/GlobalISel: Implement select for G_INSERT
Re-commit r344310.
Reviewers: arsenm
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D53116
llvm-svn: 355159
2019-03-01 01:50:26 +01:00
|
|
|
bool selectG_INSERT(MachineInstr &I) const;
|
2020-01-12 18:32:03 +01:00
|
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|
|
|
|
|
|
bool selectInterpP1F16(MachineInstr &MI) const;
|
2020-07-23 05:47:35 +02:00
|
|
|
bool selectWritelane(MachineInstr &MI) const;
|
2020-04-06 03:16:00 +02:00
|
|
|
bool selectDivScale(MachineInstr &MI) const;
|
2020-06-30 10:57:41 +02:00
|
|
|
bool selectIntrinsicIcmp(MachineInstr &MI) const;
|
2020-07-13 11:44:18 +02:00
|
|
|
bool selectBallot(MachineInstr &I) const;
|
2020-07-22 01:41:24 +02:00
|
|
|
bool selectRelocConstant(MachineInstr &I) const;
|
2020-07-26 21:43:48 +02:00
|
|
|
bool selectGroupStaticSize(MachineInstr &I) const;
|
2020-07-20 03:26:02 +02:00
|
|
|
bool selectReturnAddress(MachineInstr &I) const;
|
2019-08-13 08:26:59 +02:00
|
|
|
bool selectG_INTRINSIC(MachineInstr &I) const;
|
2019-09-19 18:26:14 +02:00
|
|
|
|
2020-01-26 09:01:53 +01:00
|
|
|
bool selectEndCfIntrinsic(MachineInstr &MI) const;
|
2020-01-05 20:26:53 +01:00
|
|
|
bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
|
2020-01-13 01:04:24 +01:00
|
|
|
bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
|
2020-01-17 04:27:31 +01:00
|
|
|
bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
|
2020-08-26 12:41:39 +02:00
|
|
|
bool selectSBarrier(MachineInstr &MI) const;
|
2019-09-19 18:26:14 +02:00
|
|
|
|
2020-02-08 05:37:54 +01:00
|
|
|
bool selectImageIntrinsic(MachineInstr &MI,
|
|
|
|
|
const AMDGPU::ImageDimIntrinsicInfo *Intr) const;
|
2019-08-13 08:26:59 +02:00
|
|
|
bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
|
2019-07-01 15:34:26 +02:00
|
|
|
int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
|
AMDGPU/GlobalISel: Implement select for G_ICMP and G_SELECT
Reviewers: arsenm
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60640
llvm-svn: 363576
2019-06-17 18:27:43 +02:00
|
|
|
bool selectG_ICMP(MachineInstr &I) const;
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
|
|
|
bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
|
|
|
|
|
void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
|
|
|
|
|
SmallVectorImpl<GEPInfo> &AddrInfo) const;
|
|
|
|
|
bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
|
2019-08-01 05:09:15 +02:00
|
|
|
|
|
|
|
|
void initM0(MachineInstr &I) const;
|
2020-08-09 21:26:30 +02:00
|
|
|
bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) const;
|
2020-02-10 04:32:44 +01:00
|
|
|
bool selectG_AMDGPU_ATOMIC_CMPXCHG(MachineInstr &I) const;
|
AMDGPU/GlobalISel: Implement select for G_ICMP and G_SELECT
Reviewers: arsenm
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60640
llvm-svn: 363576
2019-06-17 18:27:43 +02:00
|
|
|
bool selectG_SELECT(MachineInstr &I) const;
|
2019-07-01 17:39:27 +02:00
|
|
|
bool selectG_BRCOND(MachineInstr &I) const;
|
2020-07-31 22:01:38 +02:00
|
|
|
bool selectG_GLOBAL_VALUE(MachineInstr &I) const;
|
2020-05-16 00:33:01 +02:00
|
|
|
bool selectG_PTRMASK(MachineInstr &I) const;
|
2020-01-02 22:45:33 +01:00
|
|
|
bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
|
2020-01-03 18:17:56 +01:00
|
|
|
bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
|
2020-02-16 05:56:56 +01:00
|
|
|
bool selectG_SHUFFLE_VECTOR(MachineInstr &I) const;
|
2020-09-11 00:10:52 +02:00
|
|
|
bool selectAMDGPU_BUFFER_ATOMIC_FADD(MachineInstr &I) const;
|
|
|
|
|
bool selectGlobalAtomicFaddIntrinsic(MachineInstr &I) const;
|
2020-09-17 20:44:52 +02:00
|
|
|
bool selectBVHIntrinsic(MachineInstr &I) const;
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
|
|
|
|
2020-10-27 13:29:11 +01:00
|
|
|
std::pair<Register, unsigned> selectVOP3ModsImpl(MachineOperand &Root,
|
|
|
|
|
bool AllowAbs = true) const;
|
2019-07-01 17:18:56 +02:00
|
|
|
|
2018-06-22 04:54:57 +02:00
|
|
|
InstructionSelector::ComplexRendererFns
|
|
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|
|
selectVCSRC(MachineOperand &Root) const;
|
|
|
|
|
|
AMDGPU/GlobalISel: Enable TableGen'd instruction selector
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45994
llvm-svn: 332039
2018-05-10 22:53:06 +02:00
|
|
|
InstructionSelector::ComplexRendererFns
|
|
|
|
|
selectVSRC0(MachineOperand &Root) const;
|
|
|
|
|
|
2018-05-11 07:44:16 +02:00
|
|
|
InstructionSelector::ComplexRendererFns
|
|
|
|
|
selectVOP3Mods0(MachineOperand &Root) const;
|
2018-06-14 00:30:47 +02:00
|
|
|
InstructionSelector::ComplexRendererFns
|
2020-10-27 13:29:11 +01:00
|
|
|
selectVOP3BMods0(MachineOperand &Root) const;
|
|
|
|
|
InstructionSelector::ComplexRendererFns
|
2018-06-22 04:34:29 +02:00
|
|
|
selectVOP3OMods(MachineOperand &Root) const;
|
|
|
|
|
InstructionSelector::ComplexRendererFns
|
2018-06-14 00:30:47 +02:00
|
|
|
selectVOP3Mods(MachineOperand &Root) const;
|
2020-10-27 13:29:11 +01:00
|
|
|
InstructionSelector::ComplexRendererFns
|
|
|
|
|
selectVOP3BMods(MachineOperand &Root) const;
|
2020-01-26 06:25:35 +01:00
|
|
|
|
|
|
|
|
ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const;
|
|
|
|
|
|
2020-01-07 18:21:18 +01:00
|
|
|
InstructionSelector::ComplexRendererFns
|
|
|
|
|
selectVOP3Mods_nnan(MachineOperand &Root) const;
|
2018-05-11 07:44:16 +02:00
|
|
|
|
2019-09-01 04:39:00 +02:00
|
|
|
std::pair<Register, unsigned>
|
|
|
|
|
selectVOP3PModsImpl(Register Src, const MachineRegisterInfo &MRI) const;
|
|
|
|
|
|
|
|
|
|
InstructionSelector::ComplexRendererFns
|
|
|
|
|
selectVOP3PMods(MachineOperand &Root) const;
|
|
|
|
|
|
2019-09-09 20:29:37 +02:00
|
|
|
InstructionSelector::ComplexRendererFns
|
|
|
|
|
selectVOP3OpSelMods(MachineOperand &Root) const;
|
|
|
|
|
|
AMDGPU/GlobalISel: Move SMRD selection logic to TableGen
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: volkan, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D52922
llvm-svn: 354516
2019-02-20 22:02:37 +01:00
|
|
|
InstructionSelector::ComplexRendererFns
|
|
|
|
|
selectSmrdImm(MachineOperand &Root) const;
|
|
|
|
|
InstructionSelector::ComplexRendererFns
|
|
|
|
|
selectSmrdImm32(MachineOperand &Root) const;
|
|
|
|
|
InstructionSelector::ComplexRendererFns
|
|
|
|
|
selectSmrdSgpr(MachineOperand &Root) const;
|
|
|
|
|
|
2019-07-16 20:05:29 +02:00
|
|
|
template <bool Signed>
|
2020-09-11 00:10:52 +02:00
|
|
|
std::pair<Register, int>
|
2019-07-16 20:05:29 +02:00
|
|
|
selectFlatOffsetImpl(MachineOperand &Root) const;
|
2020-09-11 00:10:52 +02:00
|
|
|
|
2019-07-16 20:05:29 +02:00
|
|
|
InstructionSelector::ComplexRendererFns
|
|
|
|
|
selectFlatOffset(MachineOperand &Root) const;
|
|
|
|
|
InstructionSelector::ComplexRendererFns
|
|
|
|
|
selectFlatOffsetSigned(MachineOperand &Root) const;
|
|
|
|
|
|
2020-08-16 17:18:52 +02:00
|
|
|
InstructionSelector::ComplexRendererFns
|
|
|
|
|
selectGlobalSAddr(MachineOperand &Root) const;
|
|
|
|
|
|
2019-07-16 21:22:21 +02:00
|
|
|
InstructionSelector::ComplexRendererFns
|
|
|
|
|
selectMUBUFScratchOffen(MachineOperand &Root) const;
|
|
|
|
|
InstructionSelector::ComplexRendererFns
|
|
|
|
|
selectMUBUFScratchOffset(MachineOperand &Root) const;
|
|
|
|
|
|
2020-11-02 14:05:15 +01:00
|
|
|
bool isDSOffsetLegal(Register Base, int64_t Offset) const;
|
|
|
|
|
bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1,
|
|
|
|
|
unsigned Size) const;
|
2020-01-17 04:27:31 +01:00
|
|
|
|
|
|
|
|
std::pair<Register, unsigned>
|
2020-02-07 17:29:23 +01:00
|
|
|
selectDS1Addr1OffsetImpl(MachineOperand &Root) const;
|
2019-08-01 02:53:38 +02:00
|
|
|
InstructionSelector::ComplexRendererFns
|
|
|
|
|
selectDS1Addr1Offset(MachineOperand &Root) const;
|
2020-02-07 17:29:23 +01:00
|
|
|
|
[AMDGPU][GlobalISel] Select 8-byte LDS Ops with 4-byte alignment
Reviewers: arsenm
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73585
2020-01-07 22:13:05 +01:00
|
|
|
InstructionSelector::ComplexRendererFns
|
|
|
|
|
selectDS64Bit4ByteAligned(MachineOperand &Root) const;
|
2019-08-01 02:53:38 +02:00
|
|
|
|
2020-08-21 11:42:49 +02:00
|
|
|
InstructionSelector::ComplexRendererFns
|
|
|
|
|
selectDS128Bit8ByteAligned(MachineOperand &Root) const;
|
|
|
|
|
|
2020-11-02 14:05:15 +01:00
|
|
|
std::pair<Register, unsigned> selectDSReadWrite2Impl(MachineOperand &Root,
|
|
|
|
|
unsigned size) const;
|
2020-08-21 11:42:49 +02:00
|
|
|
InstructionSelector::ComplexRendererFns
|
2020-11-02 14:05:15 +01:00
|
|
|
selectDSReadWrite2(MachineOperand &Root, unsigned size) const;
|
2020-08-21 11:42:49 +02:00
|
|
|
|
2020-01-18 03:28:58 +01:00
|
|
|
std::pair<Register, int64_t>
|
|
|
|
|
getPtrBaseWithConstantOffset(Register Root,
|
|
|
|
|
const MachineRegisterInfo &MRI) const;
|
|
|
|
|
|
|
|
|
|
// Parse out a chain of up to two g_ptr_add instructions.
|
|
|
|
|
// g_ptr_add (n0, _)
|
|
|
|
|
// g_ptr_add (n0, (n1 = g_ptr_add n2, n3))
|
|
|
|
|
struct MUBUFAddressData {
|
|
|
|
|
Register N0, N2, N3;
|
|
|
|
|
int64_t Offset = 0;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
bool shouldUseAddr64(MUBUFAddressData AddrData) const;
|
|
|
|
|
|
|
|
|
|
void splitIllegalMUBUFOffset(MachineIRBuilder &B,
|
|
|
|
|
Register &SOffset, int64_t &ImmOffset) const;
|
|
|
|
|
|
|
|
|
|
MUBUFAddressData parseMUBUFAddress(Register Src) const;
|
|
|
|
|
|
2020-01-24 17:45:33 +01:00
|
|
|
bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
|
|
|
|
|
Register &RSrcReg, Register &SOffset,
|
|
|
|
|
int64_t &Offset) const;
|
|
|
|
|
|
|
|
|
|
bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
|
|
|
|
|
Register &SOffset, int64_t &Offset) const;
|
|
|
|
|
|
2020-01-22 22:56:48 +01:00
|
|
|
InstructionSelector::ComplexRendererFns
|
|
|
|
|
selectMUBUFAddr64(MachineOperand &Root) const;
|
|
|
|
|
|
2020-01-18 03:28:58 +01:00
|
|
|
InstructionSelector::ComplexRendererFns
|
|
|
|
|
selectMUBUFOffset(MachineOperand &Root) const;
|
|
|
|
|
|
2020-01-24 17:55:46 +01:00
|
|
|
InstructionSelector::ComplexRendererFns
|
|
|
|
|
selectMUBUFOffsetAtomic(MachineOperand &Root) const;
|
|
|
|
|
|
|
|
|
|
InstructionSelector::ComplexRendererFns
|
|
|
|
|
selectMUBUFAddr64Atomic(MachineOperand &Root) const;
|
|
|
|
|
|
2020-01-30 02:34:32 +01:00
|
|
|
ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const;
|
|
|
|
|
ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const;
|
|
|
|
|
|
TableGen/GlobalISel: Add way for SDNodeXForm to work on timm
The current implementation assumes there is an instruction associated
with the transform, but this is not the case for
timm/TargetConstant/immarg values. These transforms should directly
operate on a specific MachineOperand in the source
instruction. TableGen would assert if you attempted to define an
equivalent GISDNodeXFormEquiv using timm when it failed to find the
instruction matcher.
Specially recognize SDNodeXForms on timm, and pass the operand index
to the render function.
Ideally this would be a separate render function type that looks like
void renderFoo(MachineInstrBuilder, const MachineOperand&), but this
proved to be somewhat mechanically painful. Add an optional operand
index which will only be passed if the transform should only look at
the one source operand.
Theoretically it would also be possible to only ever pass the
MachineOperand, and the existing renderers would check the parent. I
think that would be somewhat ugly for the standard usage which may
want to inspect other operands, and I also think MachineOperand should
eventually not carry a pointer to the parent instruction.
Use it in one sample pattern. This isn't a great example, since the
transform exists to satisfy DAG type constraints. This could also be
avoided by just changing the MachineInstr's arbitrary choice of
operand type from i16 to i32. Other patterns have nontrivial uses, but
this serves as the simplest example.
One flaw this still has is if you try to use an SDNodeXForm defined
for imm, but the source pattern uses timm, you still see the "Failed
to lookup instruction" assert. However, there is now a way to avoid
it.
2020-01-08 18:53:15 +01:00
|
|
|
void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
|
|
|
|
|
int OpIdx = -1) const;
|
2019-10-01 04:07:25 +02:00
|
|
|
|
2020-01-14 00:18:56 +01:00
|
|
|
void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
|
|
|
|
|
int OpIdx) const;
|
|
|
|
|
|
2020-01-17 16:22:36 +01:00
|
|
|
void renderTruncTImm1(MachineInstrBuilder &MIB, const MachineInstr &MI,
|
2020-01-14 00:18:56 +01:00
|
|
|
int OpIdx) const {
|
|
|
|
|
renderTruncTImm(MIB, MI, OpIdx);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void renderTruncTImm8(MachineInstrBuilder &MIB, const MachineInstr &MI,
|
|
|
|
|
int OpIdx) const {
|
|
|
|
|
renderTruncTImm(MIB, MI, OpIdx);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void renderTruncTImm16(MachineInstrBuilder &MIB, const MachineInstr &MI,
|
|
|
|
|
int OpIdx) const {
|
|
|
|
|
renderTruncTImm(MIB, MI, OpIdx);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void renderTruncTImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
|
|
|
|
|
int OpIdx) const {
|
|
|
|
|
renderTruncTImm(MIB, MI, OpIdx);
|
|
|
|
|
}
|
2020-01-07 17:29:05 +01:00
|
|
|
|
TableGen/GlobalISel: Add way for SDNodeXForm to work on timm
The current implementation assumes there is an instruction associated
with the transform, but this is not the case for
timm/TargetConstant/immarg values. These transforms should directly
operate on a specific MachineOperand in the source
instruction. TableGen would assert if you attempted to define an
equivalent GISDNodeXFormEquiv using timm when it failed to find the
instruction matcher.
Specially recognize SDNodeXForms on timm, and pass the operand index
to the render function.
Ideally this would be a separate render function type that looks like
void renderFoo(MachineInstrBuilder, const MachineOperand&), but this
proved to be somewhat mechanically painful. Add an optional operand
index which will only be passed if the transform should only look at
the one source operand.
Theoretically it would also be possible to only ever pass the
MachineOperand, and the existing renderers would check the parent. I
think that would be somewhat ugly for the standard usage which may
want to inspect other operands, and I also think MachineOperand should
eventually not carry a pointer to the parent instruction.
Use it in one sample pattern. This isn't a great example, since the
transform exists to satisfy DAG type constraints. This could also be
avoided by just changing the MachineInstr's arbitrary choice of
operand type from i16 to i32. Other patterns have nontrivial uses, but
this serves as the simplest example.
One flaw this still has is if you try to use an SDNodeXForm defined
for imm, but the source pattern uses timm, you still see the "Failed
to lookup instruction" assert. However, there is now a way to avoid
it.
2020-01-08 18:53:15 +01:00
|
|
|
void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
|
|
|
|
|
int OpIdx) const;
|
2020-01-07 17:45:10 +01:00
|
|
|
|
TableGen/GlobalISel: Add way for SDNodeXForm to work on timm
The current implementation assumes there is an instruction associated
with the transform, but this is not the case for
timm/TargetConstant/immarg values. These transforms should directly
operate on a specific MachineOperand in the source
instruction. TableGen would assert if you attempted to define an
equivalent GISDNodeXFormEquiv using timm when it failed to find the
instruction matcher.
Specially recognize SDNodeXForms on timm, and pass the operand index
to the render function.
Ideally this would be a separate render function type that looks like
void renderFoo(MachineInstrBuilder, const MachineOperand&), but this
proved to be somewhat mechanically painful. Add an optional operand
index which will only be passed if the transform should only look at
the one source operand.
Theoretically it would also be possible to only ever pass the
MachineOperand, and the existing renderers would check the parent. I
think that would be somewhat ugly for the standard usage which may
want to inspect other operands, and I also think MachineOperand should
eventually not carry a pointer to the parent instruction.
Use it in one sample pattern. This isn't a great example, since the
transform exists to satisfy DAG type constraints. This could also be
avoided by just changing the MachineInstr's arbitrary choice of
operand type from i16 to i32. Other patterns have nontrivial uses, but
this serves as the simplest example.
One flaw this still has is if you try to use an SDNodeXForm defined
for imm, but the source pattern uses timm, you still see the "Failed
to lookup instruction" assert. However, there is now a way to avoid
it.
2020-01-08 18:53:15 +01:00
|
|
|
void renderBitcastImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
|
|
|
|
|
int OpIdx) const;
|
|
|
|
|
|
|
|
|
|
void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
|
|
|
|
|
int OpIdx) const;
|
2019-09-19 06:29:20 +02:00
|
|
|
void renderExtractGLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
|
|
|
|
|
int OpIdx) const;
|
|
|
|
|
void renderExtractSLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
|
|
|
|
|
int OpIdx) const;
|
|
|
|
|
void renderExtractDLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
|
|
|
|
|
int OpIdx) const;
|
|
|
|
|
void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI,
|
|
|
|
|
int OpIdx) const;
|
2020-07-31 22:01:38 +02:00
|
|
|
void renderFrameIndex(MachineInstrBuilder &MIB, const MachineInstr &MI,
|
|
|
|
|
int OpIdx) const;
|
2020-01-07 18:38:35 +01:00
|
|
|
|
2020-01-06 20:39:13 +01:00
|
|
|
bool isInlineImmediate16(int64_t Imm) const;
|
|
|
|
|
bool isInlineImmediate32(int64_t Imm) const;
|
|
|
|
|
bool isInlineImmediate64(int64_t Imm) const;
|
|
|
|
|
bool isInlineImmediate(const APFloat &Imm) const;
|
|
|
|
|
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
|
|
|
const SIInstrInfo &TII;
|
|
|
|
|
const SIRegisterInfo &TRI;
|
|
|
|
|
const AMDGPURegisterBankInfo &RBI;
|
AMDGPU/GlobalISel: Enable TableGen'd instruction selector
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45994
llvm-svn: 332039
2018-05-10 22:53:06 +02:00
|
|
|
const AMDGPUTargetMachine &TM;
|
2018-07-11 22:59:01 +02:00
|
|
|
const GCNSubtarget &STI;
|
AMDGPU/GlobalISel: Enable TableGen'd instruction selector
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45994
llvm-svn: 332039
2018-05-10 22:53:06 +02:00
|
|
|
bool EnableLateStructurizeCFG;
|
|
|
|
|
#define GET_GLOBALISEL_PREDICATES_DECL
|
2018-07-11 22:59:01 +02:00
|
|
|
#define AMDGPUSubtarget GCNSubtarget
|
AMDGPU/GlobalISel: Enable TableGen'd instruction selector
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45994
llvm-svn: 332039
2018-05-10 22:53:06 +02:00
|
|
|
#include "AMDGPUGenGlobalISel.inc"
|
|
|
|
|
#undef GET_GLOBALISEL_PREDICATES_DECL
|
2018-07-11 22:59:01 +02:00
|
|
|
#undef AMDGPUSubtarget
|
AMDGPU/GlobalISel: Enable TableGen'd instruction selector
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45994
llvm-svn: 332039
2018-05-10 22:53:06 +02:00
|
|
|
|
|
|
|
|
#define GET_GLOBALISEL_TEMPORARIES_DECL
|
|
|
|
|
#include "AMDGPUGenGlobalISel.inc"
|
|
|
|
|
#undef GET_GLOBALISEL_TEMPORARIES_DECL
|
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
llvm-svn: 293551
2017-01-30 22:56:46 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
} // End llvm namespace.
|
|
|
|
|
#endif
|
