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llvm-mirror/test/CodeGen/R600/unaligned-load-store.ll

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R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errors SI_IF and SI_ELSE are terminators which also produce a value. For these instructions ISel always inserts a COPY to move their value to another basic block. This COPY ends up between SI_(IF|ELSE) and the S_BRANCH* instruction at the end of the block. This breaks MachineBasicBlock::getFirstTerminator() and also the machine verifier which assumes that terminators are grouped together at the end of blocks. To solve this we coalesce the copy away right after ISel to make sure there are no instructions in between terminators at the end of blocks. llvm-svn: 207591
2014-04-30 01:12:53 +02:00
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
Fix CodeGen for unaligned loads with address spaces llvm-svn: 193721
2013-10-31 00:30:05 +01:00
R600/SI: Fix broken test. There was no check prefix for the instruction lines. Match what is emitted though, although I'm pretty sure it is incorrect. llvm-svn: 214035
2014-07-26 23:21:42 +02:00
; FIXME: This is probably wrong. This probably needs to expand to 8-bit reads and writes.
Fix CodeGen for unaligned loads with address spaces llvm-svn: 193721
2013-10-31 00:30:05 +01:00
; SI-LABEL: @unaligned_load_store_i32:
R600/SI: Fix broken test. There was no check prefix for the instruction lines. Match what is emitted though, although I'm pretty sure it is incorrect. llvm-svn: 214035
2014-07-26 23:21:42 +02:00
; SI: DS_READ_U16
; SI: DS_READ_U16
; SI: DS_WRITE_B32
; SI: S_ENDPGM
Fix CodeGen for unaligned loads with address spaces llvm-svn: 193721
2013-10-31 00:30:05 +01:00
define void @unaligned_load_store_i32(i32 addrspace(3)* %p, i32 addrspace(3)* %r) nounwind {
%v = load i32 addrspace(3)* %p, align 1
store i32 %v, i32 addrspace(3)* %r, align 1
ret void
}
; SI-LABEL: @unaligned_load_store_v4i32:
R600/SI: Fix broken test. There was no check prefix for the instruction lines. Match what is emitted though, although I'm pretty sure it is incorrect. llvm-svn: 214035
2014-07-26 23:21:42 +02:00
; SI: DS_READ_U16
; SI: DS_READ_U16
; SI: DS_READ_U16
; SI: DS_READ_U16
; SI: DS_READ_U16
; SI: DS_READ_U16
; SI: DS_READ_U16
; SI: DS_READ_U16
; SI: DS_WRITE_B32
; SI: DS_WRITE_B32
; SI: DS_WRITE_B32
; SI: DS_WRITE_B32
; SI: S_ENDPGM
Fix CodeGen for unaligned loads with address spaces llvm-svn: 193721
2013-10-31 00:30:05 +01:00
define void @unaligned_load_store_v4i32(<4 x i32> addrspace(3)* %p, <4 x i32> addrspace(3)* %r) nounwind {
%v = load <4 x i32> addrspace(3)* %p, align 1
store <4 x i32> %v, <4 x i32> addrspace(3)* %r, align 1
ret void
}
Add alignment value to allowsUnalignedMemoryAccess Rename to allowsMisalignedMemoryAccess. On R600, 8 and 16 byte accesses are mostly OK with 4-byte alignment, and don't need to be split into multiple accesses. Vector loads with an alignment of the element type are not uncommon in OpenCL code. llvm-svn: 214055
2014-07-27 19:46:40 +02:00
; FIXME: This should use ds_read2_b32
; SI-LABEL: @load_lds_i64_align_4
; SI: DS_READ_B64
; SI: S_ENDPGM
define void @load_lds_i64_align_4(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 {
%val = load i64 addrspace(3)* %in, align 4
store i64 %val, i64 addrspace(1)* %out, align 8
ret void
}
; FIXME: Need to fix this case.
; define void @load_lds_i64_align_1(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 {
; %val = load i64 addrspace(3)* %in, align 1
; store i64 %val, i64 addrspace(1)* %out, align 8
; ret void
; }
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