2018-05-22 06:32:10 +00:00
|
|
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; RUN: llc -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI,GCN-NO-TONGA %s
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|
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; RUN: llc -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,GCN-TONGA %s
|
2013-10-08 18:06:36 +00:00
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|
2014-02-02 00:05:35 +00:00
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; FIXME: Broken on evergreen
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; FIXME: For some reason the 8 and 16 vectors are being stored as
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|
; individual elements instead of 128-bit stores.
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; FIXME: Why is the constant moved into the intermediate register and
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; not just directly into the vector component?
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|
2016-05-28 00:51:06 +00:00
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; GCN-LABEL: {{^}}insertelement_v4f32_0:
|
2016-06-25 00:23:00 +00:00
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; GCN: s_load_dwordx4
|
2016-05-28 00:51:06 +00:00
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; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}
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; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}
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; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}
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; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}
|
2016-11-01 22:55:07 +00:00
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; GCN-DAG: s_mov_b32 [[CONSTREG:s[0-9]+]], 0x40a00000
|
2016-06-25 00:23:00 +00:00
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; GCN-DAG: v_mov_b32_e32 v[[LOW_REG:[0-9]+]], [[CONSTREG]]
|
2016-05-28 00:51:06 +00:00
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; GCN: buffer_store_dwordx4 v{{\[}}[[LOW_REG]]:
|
2017-03-21 21:39:51 +00:00
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|
define amdgpu_kernel void @insertelement_v4f32_0(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind {
|
2014-02-02 00:05:35 +00:00
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%vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 0
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store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16
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|
ret void
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}
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|
2016-05-28 00:51:06 +00:00
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|
; GCN-LABEL: {{^}}insertelement_v4f32_1:
|
2017-03-21 21:39:51 +00:00
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define amdgpu_kernel void @insertelement_v4f32_1(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind {
|
2014-02-02 00:05:35 +00:00
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|
%vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 1
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store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16
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|
ret void
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}
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|
2016-05-28 00:51:06 +00:00
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|
; GCN-LABEL: {{^}}insertelement_v4f32_2:
|
2017-03-21 21:39:51 +00:00
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|
define amdgpu_kernel void @insertelement_v4f32_2(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind {
|
2014-02-02 00:05:35 +00:00
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|
%vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 2
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|
store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16
|
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|
ret void
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|
}
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|
2016-05-28 00:51:06 +00:00
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|
; GCN-LABEL: {{^}}insertelement_v4f32_3:
|
2017-03-21 21:39:51 +00:00
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|
define amdgpu_kernel void @insertelement_v4f32_3(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind {
|
2014-02-02 00:05:35 +00:00
|
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|
%vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 3
|
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|
|
store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16
|
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|
|
ret void
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|
|
}
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|
2016-05-28 00:51:06 +00:00
|
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|
; GCN-LABEL: {{^}}insertelement_v4i32_0:
|
2017-03-21 21:39:51 +00:00
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|
define amdgpu_kernel void @insertelement_v4i32_0(<4 x i32> addrspace(1)* %out, <4 x i32> %a) nounwind {
|
2014-02-02 00:05:35 +00:00
|
|
|
%vecins = insertelement <4 x i32> %a, i32 999, i32 0
|
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|
store <4 x i32> %vecins, <4 x i32> addrspace(1)* %out, align 16
|
|
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|
|
ret void
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|
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|
|
}
|
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|
2016-05-28 00:51:06 +00:00
|
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|
; GCN-LABEL: {{^}}insertelement_v3f32_1:
|
2017-03-21 21:39:51 +00:00
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|
define amdgpu_kernel void @insertelement_v3f32_1(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind {
|
2016-05-28 00:51:06 +00:00
|
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|
%vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 1
|
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|
store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16
|
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|
|
ret void
|
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|
|
}
|
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|
; GCN-LABEL: {{^}}insertelement_v3f32_2:
|
2017-03-21 21:39:51 +00:00
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|
define amdgpu_kernel void @insertelement_v3f32_2(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind {
|
2016-05-28 00:51:06 +00:00
|
|
|
%vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 2
|
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|
|
store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16
|
|
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|
|
ret void
|
|
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|
|
}
|
|
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|
; GCN-LABEL: {{^}}insertelement_v3f32_3:
|
2017-03-21 21:39:51 +00:00
|
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|
define amdgpu_kernel void @insertelement_v3f32_3(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind {
|
2016-05-28 00:51:06 +00:00
|
|
|
%vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 3
|
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|
|
store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16
|
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|
|
ret void
|
|
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|
|
}
|
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|
2016-07-12 08:12:16 +00:00
|
|
|
; GCN-LABEL: {{^}}insertelement_to_sgpr:
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|
; GCN-NOT: v_readfirstlane
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|
define amdgpu_ps <4 x float> @insertelement_to_sgpr() nounwind {
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|
%tmp = load <4 x i32>, <4 x i32> addrspace(2)* undef
|
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|
|
%tmp1 = insertelement <4 x i32> %tmp, i32 0, i32 0
|
2017-04-04 16:34:35 +00:00
|
|
|
%tmp2 = call <4 x float> @llvm.amdgcn.image.gather4.lz.v4f32.v2f32.v8i32(<2 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 false, i1 false, i1 false, i1 false, i1 true)
|
2016-07-12 08:12:16 +00:00
|
|
|
ret <4 x float> %tmp2
|
|
|
|
|
}
|
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|
2016-05-28 00:51:06 +00:00
|
|
|
; GCN-LABEL: {{^}}dynamic_insertelement_v2f32:
|
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|
; GCN: v_mov_b32_e32 [[CONST:v[0-9]+]], 0x40a00000
|
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|
; GCN: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]]
|
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|
|
; GCN: buffer_store_dwordx2 {{v\[}}[[LOW_RESULT_REG]]:
|
2017-03-21 21:39:51 +00:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, i32 %b) nounwind {
|
2014-02-02 00:05:35 +00:00
|
|
|
%vecins = insertelement <2 x float> %a, float 5.000000e+00, i32 %b
|
|
|
|
|
store <2 x float> %vecins, <2 x float> addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2016-05-28 00:51:06 +00:00
|
|
|
; GCN-LABEL: {{^}}dynamic_insertelement_v3f32:
|
|
|
|
|
; GCN: v_mov_b32_e32 [[CONST:v[0-9]+]], 0x40a00000
|
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|
|
; GCN: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]]
|
|
|
|
|
; GCN-DAG: buffer_store_dwordx2 {{v\[}}[[LOW_RESULT_REG]]:
|
|
|
|
|
; GCN-DAG: buffer_store_dword v
|
2017-03-21 21:39:51 +00:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %a, i32 %b) nounwind {
|
2016-05-28 00:51:06 +00:00
|
|
|
%vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 %b
|
|
|
|
|
store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}dynamic_insertelement_v4f32:
|
|
|
|
|
; GCN: v_mov_b32_e32 [[CONST:v[0-9]+]], 0x40a00000
|
|
|
|
|
; GCN: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]]
|
|
|
|
|
; GCN: buffer_store_dwordx4 {{v\[}}[[LOW_RESULT_REG]]:
|
2017-03-21 21:39:51 +00:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, i32 %b) nounwind {
|
2014-02-02 00:05:35 +00:00
|
|
|
%vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 %b
|
|
|
|
|
store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2016-05-28 00:51:06 +00:00
|
|
|
; GCN-LABEL: {{^}}dynamic_insertelement_v8f32:
|
|
|
|
|
; GCN: v_movreld_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}
|
|
|
|
|
; GCN: buffer_store_dwordx4
|
|
|
|
|
; GCN: buffer_store_dwordx4
|
2017-03-21 21:39:51 +00:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, i32 %b) nounwind {
|
2014-02-02 00:05:35 +00:00
|
|
|
%vecins = insertelement <8 x float> %a, float 5.000000e+00, i32 %b
|
|
|
|
|
store <8 x float> %vecins, <8 x float> addrspace(1)* %out, align 32
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2016-05-28 00:51:06 +00:00
|
|
|
; GCN-LABEL: {{^}}dynamic_insertelement_v16f32:
|
|
|
|
|
; GCN: v_movreld_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}
|
|
|
|
|
; GCN: buffer_store_dwordx4
|
|
|
|
|
; GCN: buffer_store_dwordx4
|
|
|
|
|
; GCN: buffer_store_dwordx4
|
|
|
|
|
; GCN: buffer_store_dwordx4
|
2017-03-21 21:39:51 +00:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, i32 %b) nounwind {
|
2014-02-02 00:05:35 +00:00
|
|
|
%vecins = insertelement <16 x float> %a, float 5.000000e+00, i32 %b
|
|
|
|
|
store <16 x float> %vecins, <16 x float> addrspace(1)* %out, align 64
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2016-05-28 00:51:06 +00:00
|
|
|
; GCN-LABEL: {{^}}dynamic_insertelement_v2i32:
|
|
|
|
|
; GCN: v_movreld_b32
|
|
|
|
|
; GCN: buffer_store_dwordx2
|
2017-03-21 21:39:51 +00:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, i32 %b) nounwind {
|
2014-02-02 00:05:35 +00:00
|
|
|
%vecins = insertelement <2 x i32> %a, i32 5, i32 %b
|
|
|
|
|
store <2 x i32> %vecins, <2 x i32> addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2016-05-28 00:51:06 +00:00
|
|
|
; GCN-LABEL: {{^}}dynamic_insertelement_v3i32:
|
2016-07-19 00:35:03 +00:00
|
|
|
; GCN: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], 5
|
2016-05-28 00:51:06 +00:00
|
|
|
; GCN-DAG: buffer_store_dwordx2 {{v\[}}[[LOW_RESULT_REG]]:
|
|
|
|
|
; GCN-DAG: buffer_store_dword v
|
2017-03-21 21:39:51 +00:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> %a, i32 %b) nounwind {
|
2016-05-28 00:51:06 +00:00
|
|
|
%vecins = insertelement <3 x i32> %a, i32 5, i32 %b
|
|
|
|
|
store <3 x i32> %vecins, <3 x i32> addrspace(1)* %out, align 16
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}dynamic_insertelement_v4i32:
|
2016-07-19 00:35:03 +00:00
|
|
|
; GCN: s_load_dword [[SVAL:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, {{0x12|0x48}}
|
|
|
|
|
; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[SVAL]]
|
|
|
|
|
; GCN: v_movreld_b32_e32 v{{[0-9]+}}, [[VVAL]]
|
2016-05-28 00:51:06 +00:00
|
|
|
; GCN: buffer_store_dwordx4
|
2017-03-21 21:39:51 +00:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, i32 %b, i32 %val) nounwind {
|
2016-07-19 00:35:03 +00:00
|
|
|
%vecins = insertelement <4 x i32> %a, i32 %val, i32 %b
|
2014-02-02 00:05:35 +00:00
|
|
|
store <4 x i32> %vecins, <4 x i32> addrspace(1)* %out, align 16
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2016-05-28 00:51:06 +00:00
|
|
|
; GCN-LABEL: {{^}}dynamic_insertelement_v8i32:
|
|
|
|
|
; GCN: v_movreld_b32
|
|
|
|
|
; GCN: buffer_store_dwordx4
|
|
|
|
|
; GCN: buffer_store_dwordx4
|
2017-03-21 21:39:51 +00:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, i32 %b) nounwind {
|
2014-02-02 00:05:35 +00:00
|
|
|
%vecins = insertelement <8 x i32> %a, i32 5, i32 %b
|
|
|
|
|
store <8 x i32> %vecins, <8 x i32> addrspace(1)* %out, align 32
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2016-05-28 00:51:06 +00:00
|
|
|
; GCN-LABEL: {{^}}dynamic_insertelement_v16i32:
|
|
|
|
|
; GCN: v_movreld_b32
|
|
|
|
|
; GCN: buffer_store_dwordx4
|
|
|
|
|
; GCN: buffer_store_dwordx4
|
|
|
|
|
; GCN: buffer_store_dwordx4
|
|
|
|
|
; GCN: buffer_store_dwordx4
|
2017-03-21 21:39:51 +00:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v16i32(<16 x i32> addrspace(1)* %out, <16 x i32> %a, i32 %b) nounwind {
|
2014-02-02 00:05:35 +00:00
|
|
|
%vecins = insertelement <16 x i32> %a, i32 5, i32 %b
|
|
|
|
|
store <16 x i32> %vecins, <16 x i32> addrspace(1)* %out, align 64
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2016-05-28 00:51:06 +00:00
|
|
|
; GCN-LABEL: {{^}}dynamic_insertelement_v2i16:
|
2017-03-21 21:39:51 +00:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %a, i32 %b) nounwind {
|
2014-02-02 00:05:35 +00:00
|
|
|
%vecins = insertelement <2 x i16> %a, i16 5, i32 %b
|
|
|
|
|
store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2016-05-28 00:51:06 +00:00
|
|
|
; GCN-LABEL: {{^}}dynamic_insertelement_v3i16:
|
2017-03-21 21:39:51 +00:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %a, i32 %b) nounwind {
|
2016-05-28 00:51:06 +00:00
|
|
|
%vecins = insertelement <3 x i16> %a, i16 5, i32 %b
|
|
|
|
|
store <3 x i16> %vecins, <3 x i16> addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}dynamic_insertelement_v2i8:
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 09:54:49 +00:00
|
|
|
; VI: s_load_dword [[LOAD:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
|
|
|
|
|
; VI-NEXT: s_load_dword [[IDX:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
|
|
|
|
|
; VI-NOT: _load
|
|
|
|
|
; VI: s_lshr_b32 [[ELT1:s[0-9]+]], [[LOAD]], 8
|
2018-06-05 19:52:46 +00:00
|
|
|
; VI: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 3
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 09:54:49 +00:00
|
|
|
; VI: v_lshlrev_b16_e64 [[ELT1_SHIFT:v[0-9]+]], 8, [[ELT1]]
|
|
|
|
|
; VI: s_and_b32 [[ELT0:s[0-9]+]], [[LOAD]], 0xff{{$}}
|
|
|
|
|
; VI: v_lshlrev_b16_e64 [[MASK:v[0-9]+]], [[SCALED_IDX]], -1
|
|
|
|
|
|
|
|
|
|
; VI: v_xor_b32_e32 [[NOT:v[0-9]+]], -1, [[MASK]]
|
|
|
|
|
; VI: v_or_b32_e32 [[BUILD_VECTOR:v[0-9]+]], [[ELT0]], [[ELT1_SHIFT]]
|
|
|
|
|
|
|
|
|
|
; VI: v_and_b32_e32 [[AND1:v[0-9]+]], [[NOT]], [[BUILD_VECTOR]]
|
|
|
|
|
; VI-DAG: v_and_b32_e32 [[INSERT:v[0-9]+]], 5, [[MASK]]
|
|
|
|
|
; VI: v_or_b32_e32 [[OR:v[0-9]+]], [[INSERT]], [[BUILD_VECTOR]]
|
2018-06-05 19:52:46 +00:00
|
|
|
; VI: buffer_store_short [[OR]]
|
2017-03-21 21:39:51 +00:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v2i8(<2 x i8> addrspace(1)* %out, <2 x i8> %a, i32 %b) nounwind {
|
2014-02-02 00:05:35 +00:00
|
|
|
%vecins = insertelement <2 x i8> %a, i8 5, i32 %b
|
|
|
|
|
store <2 x i8> %vecins, <2 x i8> addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 09:54:49 +00:00
|
|
|
; FIXME: post legalize i16 and i32 shifts aren't merged because of
|
|
|
|
|
; isTypeDesirableForOp in SimplifyDemandedBits
|
|
|
|
|
|
2016-05-28 00:51:06 +00:00
|
|
|
; GCN-LABEL: {{^}}dynamic_insertelement_v3i8:
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 09:54:49 +00:00
|
|
|
; VI: s_load_dword [[LOAD:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
|
|
|
|
|
; VI-NEXT: s_load_dword [[IDX:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
|
|
|
|
|
; VI-NOT: _load
|
|
|
|
|
|
|
|
|
|
; VI: s_lshr_b32 [[VEC_HI:s[0-9]+]], [[LOAD]], 8
|
|
|
|
|
; VI: v_lshlrev_b16_e64 [[ELT2:v[0-9]+]], 8, [[VEC_HI]]
|
|
|
|
|
; VI: s_and_b32 [[ELT0:s[0-9]+]], [[LOAD]], 0xff{{$}}
|
|
|
|
|
; VI: v_or_b32_e32 [[BUILD_VEC:v[0-9]+]], [[VEC_HI]], [[ELT2]]
|
|
|
|
|
; VI: s_and_b32 [[ELT2:s[0-9]+]], [[LOAD]], 0xff0000{{$}}
|
|
|
|
|
|
|
|
|
|
; VI: s_mov_b32 [[MASK16:s[0-9]+]], 0xffff{{$}}
|
|
|
|
|
; VI: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 3
|
|
|
|
|
; VI: s_lshl_b32 [[SHIFTED_MASK:s[0-9]+]], [[MASK16]], [[SCALED_IDX]]
|
|
|
|
|
|
|
|
|
|
; VI: v_mov_b32_e32 [[V_ELT2:v[0-9]+]], [[ELT2]]
|
|
|
|
|
; VI: v_or_b32_sdwa [[SDWA:v[0-9]+]], [[BUILD_VEC]], [[V_ELT2]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
|
|
|
; VI: s_not_b32 [[NOT_SHIFT_MASK:s[0-9]+]], [[SHIFTED_MASK]]
|
|
|
|
|
; VI: v_and_b32_e32 [[AND_NOT_MASK:v[0-9]+]], [[NOT_SHIFT_MASK]], [[SDWA]]
|
|
|
|
|
; VI: v_lshrrev_b32_e32 [[HI2:v[0-9]+]], 16, [[AND_NOT_MASK]]
|
|
|
|
|
; VI: v_bfi_b32 [[BFI:v[0-9]+]], [[SCALED_IDX]], 5, [[SDWA]]
|
|
|
|
|
; VI: buffer_store_short [[BFI]]
|
|
|
|
|
; VI: buffer_store_byte [[HI2]]
|
2017-03-21 21:39:51 +00:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v3i8(<3 x i8> addrspace(1)* %out, <3 x i8> %a, i32 %b) nounwind {
|
2016-05-28 00:51:06 +00:00
|
|
|
%vecins = insertelement <3 x i8> %a, i8 5, i32 %b
|
|
|
|
|
store <3 x i8> %vecins, <3 x i8> addrspace(1)* %out, align 4
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}dynamic_insertelement_v4i8:
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 09:54:49 +00:00
|
|
|
; VI: s_load_dword [[VEC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
|
|
|
|
|
; VI-NEXT: s_load_dword [[IDX:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
|
|
|
|
|
; VI-NOT: _load
|
|
|
|
|
|
|
|
|
|
; VI: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], 8
|
|
|
|
|
; VI: v_lshlrev_b16_e64 [[ELT2:v[0-9]+]], 8, [[ELT1]]
|
|
|
|
|
; VI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0xff{{$}}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
; VI: s_lshr_b32 [[ELT3:s[0-9]+]], [[VEC]], 24
|
|
|
|
|
; VI: s_lshr_b32 [[ELT2:s[0-9]+]], [[VEC]], 16
|
|
|
|
|
; VI: v_lshlrev_b16_e64 v{{[0-9]+}}, 8, [[ELT3]]
|
|
|
|
|
; VI: v_or_b32_e32
|
|
|
|
|
; VI: v_or_b32_sdwa
|
2018-06-05 19:52:46 +00:00
|
|
|
; VI-DAG: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 3
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 09:54:49 +00:00
|
|
|
; VI: v_or_b32_sdwa
|
|
|
|
|
; VI: s_lshl_b32
|
|
|
|
|
; VI: v_bfi_b32
|
2017-03-21 21:39:51 +00:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> %a, i32 %b) nounwind {
|
2014-02-02 00:05:35 +00:00
|
|
|
%vecins = insertelement <4 x i8> %a, i8 5, i32 %b
|
2016-05-28 00:51:06 +00:00
|
|
|
store <4 x i8> %vecins, <4 x i8> addrspace(1)* %out, align 4
|
2014-02-02 00:05:35 +00:00
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 09:54:49 +00:00
|
|
|
; GCN-LABEL: {{^}}s_dynamic_insertelement_v8i8:
|
|
|
|
|
; VI-NOT: {{buffer|flat|global}}
|
2018-06-05 19:52:46 +00:00
|
|
|
; VI: s_load_dword [[IDX:s[0-9]]]
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 09:54:49 +00:00
|
|
|
; VI-NOT: {{buffer|flat|global}}
|
|
|
|
|
; VI: s_load_dwordx2 [[VEC:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0x0
|
|
|
|
|
; VI-NOT: {{buffer|flat|global}}
|
|
|
|
|
|
2018-06-05 19:52:46 +00:00
|
|
|
; VI-DAG: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 3
|
|
|
|
|
; VI-DAG: s_mov_b32 s[[MASK_HI:[0-9]+]], 0
|
|
|
|
|
; VI-DAG: s_mov_b32 s[[MASK_LO:[0-9]+]], 0xffff
|
|
|
|
|
; VI: s_lshl_b64 s{{\[}}[[MASK_SHIFT_LO:[0-9]+]]:[[MASK_SHIFT_HI:[0-9]+]]{{\]}}, s{{\[}}[[MASK_LO]]:[[MASK_HI]]{{\]}}, [[SCALED_IDX]]
|
|
|
|
|
; VI: s_not_b64 [[NOT_MASK:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[MASK_SHIFT_LO]]:[[MASK_SHIFT_HI]]{{\]}}
|
|
|
|
|
; VI: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], [[NOT_MASK]], [[VEC]]
|
|
|
|
|
; VI: s_and_b32 s[[INS:[0-9]+]], s[[MASK_SHIFT_LO]], 5
|
|
|
|
|
; VI: s_or_b64 s{{\[}}[[RESULT0:[0-9]+]]:[[RESULT1:[0-9]+]]{{\]}}, s{{\[}}[[INS]]:[[MASK_HI]]{{\]}}, [[AND]]
|
|
|
|
|
; VI: v_mov_b32_e32 v[[V_RESULT0:[0-9]+]], s[[RESULT0]]
|
|
|
|
|
; VI: v_mov_b32_e32 v[[V_RESULT1:[0-9]+]], s[[RESULT1]]
|
|
|
|
|
; VI: buffer_store_dwordx2 v{{\[}}[[V_RESULT0]]:[[V_RESULT1]]{{\]}}
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 09:54:49 +00:00
|
|
|
define amdgpu_kernel void @s_dynamic_insertelement_v8i8(<8 x i8> addrspace(1)* %out, <8 x i8> addrspace(4)* %a.ptr, i32 %b) nounwind {
|
|
|
|
|
%a = load <8 x i8>, <8 x i8> addrspace(4)* %a.ptr, align 4
|
2014-02-02 00:05:35 +00:00
|
|
|
%vecins = insertelement <8 x i8> %a, i8 5, i32 %b
|
2016-05-28 00:51:06 +00:00
|
|
|
store <8 x i8> %vecins, <8 x i8> addrspace(1)* %out, align 8
|
2013-10-08 18:06:36 +00:00
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2016-05-28 00:51:06 +00:00
|
|
|
; GCN-LABEL: {{^}}dynamic_insertelement_v16i8:
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 09:54:49 +00:00
|
|
|
; GCN: s_load_dwordx2
|
|
|
|
|
; GCN: s_load_dword s
|
|
|
|
|
; GCN: s_load_dword s
|
|
|
|
|
; GCN: s_load_dword s
|
|
|
|
|
; GCN: s_load_dword s
|
|
|
|
|
; GCN: s_load_dword s
|
|
|
|
|
; GCN-NOT: _load_
|
|
|
|
|
|
2018-06-05 19:52:46 +00:00
|
|
|
|
|
|
|
|
; GCN: buffer_store_byte
|
|
|
|
|
; GCN: buffer_store_byte
|
|
|
|
|
; GCN: buffer_store_byte
|
|
|
|
|
; GCN: buffer_store_byte
|
|
|
|
|
; GCN: buffer_store_byte
|
|
|
|
|
; GCN: buffer_store_byte
|
|
|
|
|
; GCN: buffer_store_byte
|
|
|
|
|
; GCN: buffer_store_byte
|
|
|
|
|
; GCN: buffer_store_byte
|
|
|
|
|
; GCN: buffer_store_byte
|
|
|
|
|
; GCN: buffer_store_byte
|
|
|
|
|
; GCN: buffer_store_byte
|
|
|
|
|
; GCN: buffer_store_byte
|
|
|
|
|
; GCN: buffer_store_byte
|
|
|
|
|
; GCN: buffer_store_byte
|
|
|
|
|
; GCN: buffer_store_byte
|
|
|
|
|
|
|
|
|
|
; GCN: buffer_store_byte
|
|
|
|
|
; GCN: buffer_store_dwordx4
|
2017-03-21 21:39:51 +00:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v16i8(<16 x i8> addrspace(1)* %out, <16 x i8> %a, i32 %b) nounwind {
|
2014-02-02 00:05:35 +00:00
|
|
|
%vecins = insertelement <16 x i8> %a, i8 5, i32 %b
|
|
|
|
|
store <16 x i8> %vecins, <16 x i8> addrspace(1)* %out, align 16
|
2013-10-08 18:06:36 +00:00
|
|
|
ret void
|
|
|
|
|
}
|
2014-04-07 19:45:45 +00:00
|
|
|
|
|
|
|
|
; This test requires handling INSERT_SUBREG in SIFixSGPRCopies. Check that
|
|
|
|
|
; the compiler doesn't crash.
|
2016-05-28 00:51:06 +00:00
|
|
|
; GCN-LABEL: {{^}}insert_split_bb:
|
2017-03-21 21:39:51 +00:00
|
|
|
define amdgpu_kernel void @insert_split_bb(<2 x i32> addrspace(1)* %out, i32 addrspace(1)* %in, i32 %a, i32 %b) {
|
2014-04-07 19:45:45 +00:00
|
|
|
entry:
|
|
|
|
|
%0 = insertelement <2 x i32> undef, i32 %a, i32 0
|
|
|
|
|
%1 = icmp eq i32 %a, 0
|
|
|
|
|
br i1 %1, label %if, label %else
|
|
|
|
|
|
|
|
|
|
if:
|
2015-02-27 21:17:42 +00:00
|
|
|
%2 = load i32, i32 addrspace(1)* %in
|
2014-04-07 19:45:45 +00:00
|
|
|
%3 = insertelement <2 x i32> %0, i32 %2, i32 1
|
|
|
|
|
br label %endif
|
|
|
|
|
|
|
|
|
|
else:
|
[opaque pointer type] Add textual IR support for explicit type parameter to getelementptr instruction
One of several parallel first steps to remove the target type of pointers,
replacing them with a single opaque pointer type.
This adds an explicit type parameter to the gep instruction so that when the
first parameter becomes an opaque pointer type, the type to gep through is
still available to the instructions.
* This doesn't modify gep operators, only instructions (operators will be
handled separately)
* Textual IR changes only. Bitcode (including upgrade) and changing the
in-memory representation will be in separate changes.
* geps of vectors are transformed as:
getelementptr <4 x float*> %x, ...
->getelementptr float, <4 x float*> %x, ...
Then, once the opaque pointer type is introduced, this will ultimately look
like:
getelementptr float, <4 x ptr> %x
with the unambiguous interpretation that it is a vector of pointers to float.
* address spaces remain on the pointer, not the type:
getelementptr float addrspace(1)* %x
->getelementptr float, float addrspace(1)* %x
Then, eventually:
getelementptr float, ptr addrspace(1) %x
Importantly, the massive amount of test case churn has been automated by
same crappy python code. I had to manually update a few test cases that
wouldn't fit the script's model (r228970,r229196,r229197,r229198). The
python script just massages stdin and writes the result to stdout, I
then wrapped that in a shell script to handle replacing files, then
using the usual find+xargs to migrate all the files.
update.py:
import fileinput
import sys
import re
ibrep = re.compile(r"(^.*?[^%\w]getelementptr inbounds )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))")
normrep = re.compile( r"(^.*?[^%\w]getelementptr )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))")
def conv(match, line):
if not match:
return line
line = match.groups()[0]
if len(match.groups()[5]) == 0:
line += match.groups()[2]
line += match.groups()[3]
line += ", "
line += match.groups()[1]
line += "\n"
return line
for line in sys.stdin:
if line.find("getelementptr ") == line.find("getelementptr inbounds"):
if line.find("getelementptr inbounds") != line.find("getelementptr inbounds ("):
line = conv(re.match(ibrep, line), line)
elif line.find("getelementptr ") != line.find("getelementptr ("):
line = conv(re.match(normrep, line), line)
sys.stdout.write(line)
apply.sh:
for name in "$@"
do
python3 `dirname "$0"`/update.py < "$name" > "$name.tmp" && mv "$name.tmp" "$name"
rm -f "$name.tmp"
done
The actual commands:
From llvm/src:
find test/ -name *.ll | xargs ./apply.sh
From llvm/src/tools/clang:
find test/ -name *.mm -o -name *.m -o -name *.cpp -o -name *.c | xargs -I '{}' ../../apply.sh "{}"
From llvm/src/tools/polly:
find test/ -name *.ll | xargs ./apply.sh
After that, check-all (with llvm, clang, clang-tools-extra, lld,
compiler-rt, and polly all checked out).
The extra 'rm' in the apply.sh script is due to a few files in clang's test
suite using interesting unicode stuff that my python script was throwing
exceptions on. None of those files needed to be migrated, so it seemed
sufficient to ignore those cases.
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7636
llvm-svn: 230786
2015-02-27 19:29:02 +00:00
|
|
|
%4 = getelementptr i32, i32 addrspace(1)* %in, i32 1
|
2015-02-27 21:17:42 +00:00
|
|
|
%5 = load i32, i32 addrspace(1)* %4
|
2014-04-07 19:45:45 +00:00
|
|
|
%6 = insertelement <2 x i32> %0, i32 %5, i32 1
|
|
|
|
|
br label %endif
|
|
|
|
|
|
|
|
|
|
endif:
|
|
|
|
|
%7 = phi <2 x i32> [%3, %if], [%6, %else]
|
|
|
|
|
store <2 x i32> %7, <2 x i32> addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
2014-09-19 23:02:18 +00:00
|
|
|
|
2016-05-28 00:51:06 +00:00
|
|
|
; GCN-LABEL: {{^}}dynamic_insertelement_v2f64:
|
2016-07-19 00:35:03 +00:00
|
|
|
; GCN-DAG: s_load_dwordx4 s{{\[}}[[A_ELT0:[0-9]+]]:[[A_ELT3:[0-9]+]]{{\]}}
|
|
|
|
|
; GCN-DAG: s_load_dword [[IDX:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, {{0x11|0x44}}{{$}}
|
|
|
|
|
|
2016-05-28 00:51:06 +00:00
|
|
|
; GCN-DAG: s_lshl_b32 [[SCALEDIDX:s[0-9]+]], [[IDX]], 1{{$}}
|
2015-11-25 19:58:34 +00:00
|
|
|
|
2016-05-28 00:51:06 +00:00
|
|
|
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}
|
|
|
|
|
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}
|
|
|
|
|
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}
|
|
|
|
|
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}
|
2016-07-19 00:35:03 +00:00
|
|
|
; GCN-DAG: v_mov_b32_e32 [[ELT1:v[0-9]+]], 0x40200000
|
2015-11-25 19:58:34 +00:00
|
|
|
|
2016-08-29 19:42:52 +00:00
|
|
|
; GCN-DAG: s_mov_b32 m0, [[SCALEDIDX]]
|
2016-07-19 00:35:03 +00:00
|
|
|
; GCN: v_movreld_b32_e32 v{{[0-9]+}}, 0
|
2015-11-25 19:58:34 +00:00
|
|
|
|
2016-07-19 00:35:03 +00:00
|
|
|
; Increment to next element folded into base register, but FileCheck
|
|
|
|
|
; can't do math expressions
|
|
|
|
|
|
|
|
|
|
; FIXME: Should be able to manipulate m0 directly instead of s_lshl_b32 + copy to m0
|
2015-11-25 19:58:34 +00:00
|
|
|
|
2016-05-28 00:51:06 +00:00
|
|
|
; GCN: v_movreld_b32_e32 v{{[0-9]+}}, [[ELT1]]
|
2015-11-25 19:58:34 +00:00
|
|
|
|
2016-05-28 00:51:06 +00:00
|
|
|
; GCN: buffer_store_dwordx4
|
|
|
|
|
; GCN: s_endpgm
|
2017-03-21 21:39:51 +00:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %a, i32 %b) nounwind {
|
2014-09-19 23:02:18 +00:00
|
|
|
%vecins = insertelement <2 x double> %a, double 8.0, i32 %b
|
|
|
|
|
store <2 x double> %vecins, <2 x double> addrspace(1)* %out, align 16
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2016-05-28 00:51:06 +00:00
|
|
|
; GCN-LABEL: {{^}}dynamic_insertelement_v2i64:
|
2015-11-25 19:58:34 +00:00
|
|
|
|
2016-07-19 00:35:03 +00:00
|
|
|
; GCN-DAG: v_movreld_b32_e32 v{{[0-9]+}}, 5
|
|
|
|
|
; GCN-DAG: v_movreld_b32_e32 v{{[0-9]+}}, 0
|
2015-11-25 19:58:34 +00:00
|
|
|
|
2016-05-28 00:51:06 +00:00
|
|
|
; GCN: buffer_store_dwordx4
|
|
|
|
|
; GCN: s_endpgm
|
2017-03-21 21:39:51 +00:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %a, i32 %b) nounwind {
|
2014-09-19 23:02:18 +00:00
|
|
|
%vecins = insertelement <2 x i64> %a, i64 5, i32 %b
|
|
|
|
|
store <2 x i64> %vecins, <2 x i64> addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2016-05-28 00:51:06 +00:00
|
|
|
; GCN-LABEL: {{^}}dynamic_insertelement_v3i64:
|
2017-03-21 21:39:51 +00:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v3i64(<3 x i64> addrspace(1)* %out, <3 x i64> %a, i32 %b) nounwind {
|
2016-05-28 00:51:06 +00:00
|
|
|
%vecins = insertelement <3 x i64> %a, i64 5, i32 %b
|
|
|
|
|
store <3 x i64> %vecins, <3 x i64> addrspace(1)* %out, align 32
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2015-11-25 19:58:34 +00:00
|
|
|
; FIXME: Should be able to do without stack access. The used stack
|
|
|
|
|
; space is also 2x what should be required.
|
|
|
|
|
|
2016-05-28 00:51:06 +00:00
|
|
|
; GCN-LABEL: {{^}}dynamic_insertelement_v4f64:
|
|
|
|
|
; GCN: SCRATCH_RSRC_DWORD
|
2015-11-25 19:58:34 +00:00
|
|
|
|
|
|
|
|
; Stack store
|
2016-05-28 00:51:06 +00:00
|
|
|
|
2017-02-22 21:05:25 +00:00
|
|
|
; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:32{{$}}
|
|
|
|
|
; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:48{{$}}
|
2015-11-25 19:58:34 +00:00
|
|
|
|
|
|
|
|
; Write element
|
2016-05-28 00:51:06 +00:00
|
|
|
; GCN: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}}
|
2015-11-25 19:58:34 +00:00
|
|
|
|
|
|
|
|
; Stack reload
|
2017-02-22 21:05:25 +00:00
|
|
|
; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:32{{$}}
|
|
|
|
|
; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:48{{$}}
|
2015-11-25 19:58:34 +00:00
|
|
|
|
|
|
|
|
; Store result
|
2016-05-28 00:51:06 +00:00
|
|
|
; GCN: buffer_store_dwordx4
|
|
|
|
|
; GCN: buffer_store_dwordx4
|
|
|
|
|
; GCN: s_endpgm
|
|
|
|
|
; GCN: ScratchSize: 64
|
2015-11-25 19:58:34 +00:00
|
|
|
|
2017-03-21 21:39:51 +00:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, i32 %b) nounwind {
|
2014-09-19 23:02:18 +00:00
|
|
|
%vecins = insertelement <4 x double> %a, double 8.0, i32 %b
|
|
|
|
|
store <4 x double> %vecins, <4 x double> addrspace(1)* %out, align 16
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2016-05-28 00:51:06 +00:00
|
|
|
; GCN-LABEL: {{^}}dynamic_insertelement_v8f64:
|
2016-11-16 18:42:17 +00:00
|
|
|
; GCN-DAG: SCRATCH_RSRC_DWORD
|
2015-11-25 19:58:34 +00:00
|
|
|
|
2017-02-22 21:05:25 +00:00
|
|
|
; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:64{{$}}
|
|
|
|
|
; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:80{{$}}
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; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:96{{$}}
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; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:112{{$}}
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2015-11-25 19:58:34 +00:00
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2016-05-28 00:51:06 +00:00
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; GCN: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}}
|
2015-11-25 19:58:34 +00:00
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2017-02-22 21:05:25 +00:00
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; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:64{{$}}
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; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:80{{$}}
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; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:96{{$}}
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; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:112{{$}}
|
2015-11-25 19:58:34 +00:00
|
|
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|
2016-05-28 00:51:06 +00:00
|
|
|
; GCN: buffer_store_dwordx4
|
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|
; GCN: buffer_store_dwordx4
|
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; GCN: buffer_store_dwordx4
|
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; GCN: buffer_store_dwordx4
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; GCN: s_endpgm
|
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|
; GCN: ScratchSize: 128
|
2017-04-04 16:34:35 +00:00
|
|
|
define amdgpu_kernel void @dynamic_insertelement_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %a, i32 %b) #0 {
|
2014-09-19 23:02:18 +00:00
|
|
|
%vecins = insertelement <8 x double> %a, double 8.0, i32 %b
|
|
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|
store <8 x double> %vecins, <8 x double> addrspace(1)* %out, align 16
|
|
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|
|
ret void
|
|
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|
|
}
|
2016-07-12 08:12:16 +00:00
|
|
|
|
2017-04-04 16:34:35 +00:00
|
|
|
declare <4 x float> @llvm.amdgcn.image.gather4.lz.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
|
|
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|
|
|
|
|
|
attributes #0 = { nounwind }
|
|
|
|
|
attributes #1 = { nounwind readnone }
|
