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llvm-mirror/test/MC/RISCV/priv-valid.s

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[RISCV] Enable emission of alias instructions by default This patch switches the default for -riscv-no-aliases to false and updates all affected MC and CodeGen tests. As recommended in D41071, MC tests use the canonical instructions and the CodeGen tests use the aliases. Additionally, for the f and d instructions with rounding mode, the tests for the aliased versions are moved and tightened such that they can actually detect if alias emission is enabled. (see D40902 for context) Differential Revision: https://reviews.llvm.org/D41225 Patch by Mario Werner. llvm-svn: 320797
2017-12-15 10:47:01 +01:00
# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
[RISCV] MC layer support for the instructions added in the privileged spec Adds support for the instructions added in the RISC-V privileged ISA (https://content.riscv.org/wp-content/uploads/2017/05/riscv-privileged-v1.10.pdf): uret, sret, mret, wfi, and sfence.vma. Note from the committer: I made very minor formatting changes prior to commit, which didn't seem worth creating another review round-trip for. Differential Revision: https://reviews.llvm.org/D40383 Patch by David Craven. llvm-svn: 320484
2017-12-12 16:17:45 +01:00
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
[RISCV] Enable emission of alias instructions by default This patch switches the default for -riscv-no-aliases to false and updates all affected MC and CodeGen tests. As recommended in D41071, MC tests use the canonical instructions and the CodeGen tests use the aliases. Additionally, for the f and d instructions with rounding mode, the tests for the aliased versions are moved and tightened such that they can actually detect if alias emission is enabled. (see D40902 for context) Differential Revision: https://reviews.llvm.org/D41225 Patch by Mario Werner. llvm-svn: 320797
2017-12-15 10:47:01 +01:00
# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
[RISCV] MC layer support for the instructions added in the privileged spec Adds support for the instructions added in the RISC-V privileged ISA (https://content.riscv.org/wp-content/uploads/2017/05/riscv-privileged-v1.10.pdf): uret, sret, mret, wfi, and sfence.vma. Note from the committer: I made very minor formatting changes prior to commit, which didn't seem worth creating another review round-trip for. Differential Revision: https://reviews.llvm.org/D40383 Patch by David Craven. llvm-svn: 320484
2017-12-12 16:17:45 +01:00
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
[RISCV] Enable emission of alias instructions by default This patch switches the default for -riscv-no-aliases to false and updates all affected MC and CodeGen tests. As recommended in D41071, MC tests use the canonical instructions and the CodeGen tests use the aliases. Additionally, for the f and d instructions with rounding mode, the tests for the aliased versions are moved and tightened such that they can actually detect if alias emission is enabled. (see D40902 for context) Differential Revision: https://reviews.llvm.org/D41225 Patch by Mario Werner. llvm-svn: 320797
2017-12-15 10:47:01 +01:00
# RUN: | llvm-objdump -riscv-no-aliases -d - \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
[RISCV] MC layer support for the instructions added in the privileged spec Adds support for the instructions added in the RISC-V privileged ISA (https://content.riscv.org/wp-content/uploads/2017/05/riscv-privileged-v1.10.pdf): uret, sret, mret, wfi, and sfence.vma. Note from the committer: I made very minor formatting changes prior to commit, which didn't seem worth creating another review round-trip for. Differential Revision: https://reviews.llvm.org/D40383 Patch by David Craven. llvm-svn: 320484
2017-12-12 16:17:45 +01:00
# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
[RISCV] Enable emission of alias instructions by default This patch switches the default for -riscv-no-aliases to false and updates all affected MC and CodeGen tests. As recommended in D41071, MC tests use the canonical instructions and the CodeGen tests use the aliases. Additionally, for the f and d instructions with rounding mode, the tests for the aliased versions are moved and tightened such that they can actually detect if alias emission is enabled. (see D40902 for context) Differential Revision: https://reviews.llvm.org/D41225 Patch by Mario Werner. llvm-svn: 320797
2017-12-15 10:47:01 +01:00
# RUN: | llvm-objdump -riscv-no-aliases -d - \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
[RISCV] MC layer support for the instructions added in the privileged spec Adds support for the instructions added in the RISC-V privileged ISA (https://content.riscv.org/wp-content/uploads/2017/05/riscv-privileged-v1.10.pdf): uret, sret, mret, wfi, and sfence.vma. Note from the committer: I made very minor formatting changes prior to commit, which didn't seem worth creating another review round-trip for. Differential Revision: https://reviews.llvm.org/D40383 Patch by David Craven. llvm-svn: 320484
2017-12-12 16:17:45 +01:00
# CHECK-INST: uret
# CHECK: encoding: [0x73,0x00,0x20,0x00]
uret
# CHECK-INST: sret
# CHECK: encoding: [0x73,0x00,0x20,0x10]
sret
# CHECK-INST: mret
# CHECK: encoding: [0x73,0x00,0x20,0x30]
mret
# CHECK-INST: wfi
# CHECK: encoding: [0x73,0x00,0x50,0x10]
wfi
# CHECK-INST: sfence.vma zero, zero
# CHECK: encoding: [0x73,0x00,0x00,0x12]
sfence.vma zero, zero
# CHECK-INST: sfence.vma a0, a1
# CHECK: encoding: [0x73,0x00,0xb5,0x12]
sfence.vma a0, a1
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