2017-08-01 23:20:10 +02:00
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//==- HexagonTargetTransformInfo.cpp - Hexagon specific TTI pass -*- C++ -*-==//
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2015-08-05 20:35:37 +02:00
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//
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2019-01-19 09:50:56 +01:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2015-08-05 20:35:37 +02:00
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//
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/// \file
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/// This file implements a TargetTransformInfo analysis pass specific to the
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/// Hexagon target machine. It uses the target's detailed information to provide
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/// more precise answers to certain TTI queries, while letting the target
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/// independent and default TTI implementations handle the rest.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONTARGETTRANSFORMINFO_H
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#define LLVM_LIB_TARGET_HEXAGON_HEXAGONTARGETTRANSFORMINFO_H
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#include "Hexagon.h"
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#include "HexagonSubtarget.h"
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#include "HexagonTargetMachine.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/IR/Function.h"
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namespace llvm {
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2017-08-01 23:20:10 +02:00
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class Loop;
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class ScalarEvolution;
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class User;
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class Value;
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class HexagonTTIImpl : public BasicTTIImplBase<HexagonTTIImpl> {
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using BaseT = BasicTTIImplBase<HexagonTTIImpl>;
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using TTI = TargetTransformInfo;
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friend BaseT;
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2018-04-13 22:46:50 +02:00
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const HexagonSubtarget &ST;
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const HexagonTargetLowering &TLI;
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const HexagonSubtarget *getST() const { return &ST; }
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const HexagonTargetLowering *getTLI() const { return &TLI; }
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bool useHVX() const;
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bool isTypeForHVX(Type *VecTy) const;
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2018-06-12 17:12:50 +02:00
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// Returns the number of vector elements of Ty, if Ty is a vector type,
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// or 1 if Ty is a scalar type. It is incorrect to call this function
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// with any other type.
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unsigned getTypeNumElements(Type *Ty) const;
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public:
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explicit HexagonTTIImpl(const HexagonTargetMachine *TM, const Function &F)
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: BaseT(TM, F.getParent()->getDataLayout()),
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ST(*TM->getSubtargetImpl(F)), TLI(*ST.getTargetLowering()) {}
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/// \name Scalar TTI Implementations
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/// @{
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TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const;
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// The Hexagon target can unroll loops with run-time trip counts.
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[LoopUnroll] Pass SCEV to getUnrollingPreferences hook. NFCI.
Reviewers: sanjoy, anna, reames, apilipenko, igor-laevsky, mkuper
Subscribers: jholewinski, arsenm, mzolotukhin, nemanjai, nhaehnle, javed.absar, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D34531
llvm-svn: 306554
2017-06-28 17:53:17 +02:00
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void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::UnrollingPreferences &UP);
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[NFC] Separate Peeling Properties into its own struct (re-land after minor fix)
Summary:
This patch separates the peeling specific parameters from the UnrollingPreferences,
and creates a new struct called PeelingPreferences. Functions which used the
UnrollingPreferences struct for peeling have been updated to use the PeelingPreferences struct.
Author: sidbav (Sidharth Baveja)
Reviewers: Whitney (Whitney Tsang), Meinersbur (Michael Kruse), skatkov (Serguei Katkov), ashlykov (Arkady Shlykov), bogner (Justin Bogner), hfinkel (Hal Finkel), anhtuyen (Anh Tuyen Tran), nikic (Nikita Popov)
Reviewed By: Meinersbur (Michael Kruse)
Subscribers: fhahn (Florian Hahn), hiraditya (Aditya Kumar), llvm-commits, LLVM
Tag: LLVM
Differential Revision: https://reviews.llvm.org/D80580
2020-07-10 20:38:08 +02:00
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void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::PeelingPreferences &PP);
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2018-03-26 17:32:03 +02:00
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/// Bias LSR towards creating post-increment opportunities.
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bool shouldFavorPostInc() const;
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2016-07-22 16:22:43 +02:00
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// L1 cache prefetch.
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2019-10-09 21:51:48 +02:00
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unsigned getPrefetchDistance() const override;
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unsigned getCacheLineSize() const override;
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2016-07-22 16:22:43 +02:00
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/// @}
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/// \name Vector TTI Implementations
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/// @{
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unsigned getNumberOfRegisters(bool vector) const;
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2018-03-27 19:07:52 +02:00
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unsigned getMaxInterleaveFactor(unsigned VF);
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unsigned getRegisterBitWidth(bool Vector) const;
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unsigned getMinVectorRegisterBitWidth() const;
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unsigned getMinimumVF(unsigned ElemWidth) const;
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2018-04-13 22:46:50 +02:00
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bool shouldMaximizeVectorBandwidth(bool OptSize) const {
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return true;
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}
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2018-03-27 19:07:52 +02:00
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bool supportsEfficientVectorElementLoadStore() {
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return false;
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}
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bool hasBranchDivergence() {
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return false;
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}
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bool enableAggressiveInterleaving(bool LoopHasReductions) {
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return false;
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}
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bool prefersVectorizedAddressing() {
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return false;
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}
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bool enableInterleavedAccessVectorization() {
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return true;
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}
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2018-03-27 19:07:52 +02:00
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2020-05-05 17:57:55 +02:00
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unsigned getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts,
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2020-04-29 12:39:13 +02:00
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bool Insert, bool Extract);
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unsigned getOperandsScalarizationOverhead(ArrayRef<const Value *> Args,
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unsigned VF);
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unsigned getCallInstrCost(Function *F, Type *RetTy, ArrayRef<Type*> Tys,
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TTI::TargetCostKind CostKind);
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2020-05-20 10:18:42 +02:00
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unsigned getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
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TTI::TargetCostKind CostKind);
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unsigned getAddressComputationCost(Type *Tp, ScalarEvolution *SE,
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const SCEV *S);
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2019-10-22 17:16:52 +02:00
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unsigned getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment,
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unsigned AddressSpace,
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TTI::TargetCostKind CostKind,
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const Instruction *I = nullptr);
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unsigned
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getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
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unsigned AddressSpace,
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TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency);
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unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
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Type *SubTp);
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2020-06-23 15:07:44 +02:00
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unsigned getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
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const Value *Ptr, bool VariableMask,
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Align Alignment, TTI::TargetCostKind CostKind,
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const Instruction *I);
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2020-06-26 13:00:53 +02:00
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unsigned getInterleavedMemoryOpCost(
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unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
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Align Alignment, unsigned AddressSpace,
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TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency,
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bool UseMaskForCond = false, bool UseMaskForGaps = false);
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unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
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TTI::TargetCostKind CostKind,
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const Instruction *I = nullptr);
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[ARM] Teach the Arm cost model that a Shift can be folded into other instructions
This attempts to teach the cost model in Arm that code such as:
%s = shl i32 %a, 3
%a = and i32 %s, %b
Can under Arm or Thumb2 become:
and r0, r1, r2, lsl #3
So the cost of the shift can essentially be free. To do this without
trying to artificially adjust the cost of the "and" instruction, it
needs to get the users of the shl and check if they are a type of
instruction that the shift can be folded into. And so it needs to have
access to the actual instruction in getArithmeticInstrCost, which if
available is added as an extra parameter much like getCastInstrCost.
We otherwise limit it to shifts with a single user, which should
hopefully handle most of the cases. The list of instruction that the
shift can be folded into include ADC, ADD, AND, BIC, CMP, EOR, MVN, ORR,
ORN, RSB, SBC and SUB. This translates to Add, Sub, And, Or, Xor and
ICmp.
Differential Revision: https://reviews.llvm.org/D70966
2019-12-08 16:33:24 +01:00
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unsigned getArithmeticInstrCost(
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unsigned Opcode, Type *Ty,
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2020-04-28 15:11:27 +02:00
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TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput,
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[ARM] Teach the Arm cost model that a Shift can be folded into other instructions
This attempts to teach the cost model in Arm that code such as:
%s = shl i32 %a, 3
%a = and i32 %s, %b
Can under Arm or Thumb2 become:
and r0, r1, r2, lsl #3
So the cost of the shift can essentially be free. To do this without
trying to artificially adjust the cost of the "and" instruction, it
needs to get the users of the shl and check if they are a type of
instruction that the shift can be folded into. And so it needs to have
access to the actual instruction in getArithmeticInstrCost, which if
available is added as an extra parameter much like getCastInstrCost.
We otherwise limit it to shifts with a single user, which should
hopefully handle most of the cases. The list of instruction that the
shift can be folded into include ADC, ADD, AND, BIC, CMP, EOR, MVN, ORR,
ORN, RSB, SBC and SUB. This translates to Add, Sub, And, Or, Xor and
ICmp.
Differential Revision: https://reviews.llvm.org/D70966
2019-12-08 16:33:24 +01:00
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TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
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TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
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TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
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TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,
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ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
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const Instruction *CxtI = nullptr);
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unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
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TTI::TargetCostKind CostKind,
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const Instruction *I = nullptr);
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unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
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2020-04-28 15:11:27 +02:00
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unsigned getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind) {
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return 1;
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}
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/// @}
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2016-08-19 16:22:07 +02:00
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2020-04-27 10:02:14 +02:00
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int getUserCost(const User *U, ArrayRef<const Value *> Operands,
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TTI::TargetCostKind CostKind);
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2017-06-30 22:54:24 +02:00
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// Hexagon specific decision to generate a lookup table.
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bool shouldBuildLookupTables() const;
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};
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} // end namespace llvm
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2017-08-01 23:20:10 +02:00
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#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONTARGETTRANSFORMINFO_H
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