[ModuloSchedule] Peel out prologs and epilogs, generate actual code
Summary:
This extends the PeelingModuloScheduleExpander to generate prolog and epilog code,
and correctly stitch uses through the prolog, kernel, epilog DAG.
The key concept in this patch is to ensure that all transforms are *local*; only a
function of a block and its immediate predecessor and successor. By defining the problem in this way
we can inductively rewrite the entire DAG using only local knowledge that is easy to
reason about.
For example, we assume that all prologs and epilogs are near-perfect clones of the
steady-state kernel. This means that if a block has an instruction that is predicated out,
we can redirect all users of that instruction to that equivalent instruction in our
immediate predecessor. As all blocks are clones, every instruction must have an equivalent in
every other block.
Similarly we can make the assumption by construction that if a value defined in a block is used
outside that block, the only possible user is its immediate successors. We maintain this
even for values that are used outside the loop by creating a limited form of LCSSA.
This code isn't small, but it isn't complex.
Enabled a bunch of testing from Hexagon. There are a couple of tests not enabled yet;
I'm about 80% sure there isn't buggy codegen but the tests are checking for patterns
that we don't produce. Those still need a bit more investigation. In the meantime we
(Google) are happy with the code produced by this on our downstream SMS implementation,
and believe it generates correct code.
Subscribers: mgorny, hiraditya, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68205
llvm-svn: 373462
2019-10-02 14:46:44 +02:00
|
|
|
; RUN: llc -march=hexagon -enable-pipeliner-opt-size -hexagon-initial-cfg-cleanup=0 < %s -pipeliner-experimental-cg=true | FileCheck %s
|
2018-03-12 15:01:28 +01:00
|
|
|
|
|
|
|
|
; Test that we generate the correct names for the phis in the kernel for the
|
|
|
|
|
; incoming values. In this case, the loop contains a phi and has another phi
|
|
|
|
|
; as its loop definition, and the two phis are scheduled in different stages.
|
|
|
|
|
;
|
|
|
|
|
; vreg5 = phi(x, vreg4) is scheduled in stage 1, cycle 0
|
|
|
|
|
; vreg4 = phi(y, z) is scheduled in stage 0, cycle 0
|
|
|
|
|
|
|
|
|
|
; CHECK-DAG: :[[REG0:[0-9]+]]{{.*}} = {{.*}},#17
|
|
|
|
|
; CHECK-DAG: loop0(.LBB0_[[LOOP:.]],
|
|
|
|
|
; CHECK: .LBB0_[[LOOP]]:
|
|
|
|
|
; CHECK: r{{[0-9]+}} = sxth(r[[REG0]])
|
|
|
|
|
; CHECK: endloop0
|
|
|
|
|
|
|
|
|
|
; Function Attrs: nounwind optsize
|
|
|
|
|
define void @f0() #0 {
|
|
|
|
|
b0:
|
|
|
|
|
%v0 = getelementptr [8 x i16], [8 x i16]* undef, i32 0, i32 7
|
|
|
|
|
%v1 = bitcast i16* %v0 to [8 x i16]*
|
|
|
|
|
br label %b2
|
|
|
|
|
|
|
|
|
|
b1: ; preds = %b2
|
|
|
|
|
unreachable
|
|
|
|
|
|
|
|
|
|
b2: ; preds = %b2, %b0
|
|
|
|
|
%v2 = phi i32 [ 7, %b0 ], [ %v11, %b2 ]
|
|
|
|
|
%v3 = phi i16 [ 17, %b0 ], [ %v7, %b2 ]
|
|
|
|
|
%v4 = phi i16 [ 18, %b0 ], [ %v3, %b2 ]
|
|
|
|
|
%v5 = sext i16 %v4 to i32
|
|
|
|
|
%v6 = getelementptr i16, i16* null, i32 -2
|
|
|
|
|
%v7 = load i16, i16* %v6, align 2
|
|
|
|
|
%v8 = sext i16 %v7 to i32
|
|
|
|
|
%v9 = tail call i32 @llvm.hexagon.A2.subsat(i32 %v5, i32 %v8)
|
|
|
|
|
%v10 = trunc i32 %v9 to i16
|
|
|
|
|
store i16 %v10, i16* null, align 2
|
|
|
|
|
%v11 = add nsw i32 %v2, -1
|
|
|
|
|
%v12 = icmp sgt i32 %v11, 1
|
|
|
|
|
br i1 %v12, label %b2, label %b1
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; Function Attrs: nounwind readnone
|
|
|
|
|
declare i32 @llvm.hexagon.A2.subsat(i32, i32) #1
|
|
|
|
|
|
|
|
|
|
attributes #0 = { nounwind optsize "target-cpu"="hexagonv60" }
|
|
|
|
|
attributes #1 = { nounwind readnone }
|
