llvm-mirror/test/CodeGen/X86/2007-01-08-InstrSched.ll

; PR1075
; RUN: llc < %s -mcpu=generic -mtriple=x86_64-apple-darwin -O3 | FileCheck %s

define float @foo(float %x) nounwind {
    %tmp1 = fmul float %x, 3.000000e+00
    %tmp3 = fmul float %x, 5.000000e+00
    %tmp5 = fmul float %x, 7.000000e+00
    %tmp7 = fmul float %x, 1.100000e+01
    %tmp10 = fadd float %tmp1, %tmp3
    %tmp12 = fadd float %tmp10, %tmp5
    %tmp14 = fadd float %tmp12, %tmp7
    ret float %tmp14

; CHECK: mulss
; CHECK: mulss
; CHECK: addss
; CHECK: mulss
; CHECK: addss
; CHECK: mulss
; CHECK: addss
; CHECK: ret
}
Add PR number for future reference llvm-svn: 33031 2007-01-09 01:31:52 +01:00			`; PR1075`
Instruction scheduling itinerary for Intel Atom. Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! llvm-svn: 149558 2012-02-02 00:20:51 +01:00			`; RUN: llc < %s -mcpu=generic -mtriple=x86_64-apple-darwin -O3 \| FileCheck %s`
Added a test case from PR1075. llvm-svn: 33028 2007-01-09 00:58:27 +01:00
eliminate some uses of prcontext. Any help here would be appreciated :) llvm-svn: 80520 2009-08-30 23:45:23 +02:00			`define float @foo(float %x) nounwind {`
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897 2009-06-05 00:49:04 +02:00			`%tmp1 = fmul float %x, 3.000000e+00`
			`%tmp3 = fmul float %x, 5.000000e+00`
			`%tmp5 = fmul float %x, 7.000000e+00`
			`%tmp7 = fmul float %x, 1.100000e+01`
			`%tmp10 = fadd float %tmp1, %tmp3`
			`%tmp12 = fadd float %tmp10, %tmp5`
			`%tmp14 = fadd float %tmp12, %tmp7`
Added a test case from PR1075. llvm-svn: 33028 2007-01-09 00:58:27 +01:00			`ret float %tmp14`
eliminate some uses of prcontext. Any help here would be appreciated :) llvm-svn: 80520 2009-08-30 23:45:23 +02:00
Teach two-address lowering how to unfold a load to open up commuting opportunities. For example, this lets it emit this: movq (%rax), %rcx addq %rdx, %rcx instead of this: movq %rdx, %rcx addq (%rax), %rcx in the case where %rdx has subsequent uses. It's the same number of instructions, and usually the same encoding size on x86, but it appears faster, and in general, it may allow better scheduling for the load. llvm-svn: 106493 2010-06-22 00:17:20 +02:00			`; CHECK: mulss`
			`; CHECK: mulss`
Turning off post-ra scheduling for x86. It isn't a consistent win. llvm-svn: 98810 2010-03-18 07:55:42 +01:00			`; CHECK: addss`
Teach two-address lowering how to unfold a load to open up commuting opportunities. For example, this lets it emit this: movq (%rax), %rcx addq %rdx, %rcx instead of this: movq %rdx, %rcx addq (%rax), %rcx in the case where %rdx has subsequent uses. It's the same number of instructions, and usually the same encoding size on x86, but it appears faster, and in general, it may allow better scheduling for the load. llvm-svn: 106493 2010-06-22 00:17:20 +02:00			`; CHECK: mulss`
Turning off post-ra scheduling for x86. It isn't a consistent win. llvm-svn: 98810 2010-03-18 07:55:42 +01:00			`; CHECK: addss`
Teach two-address lowering how to unfold a load to open up commuting opportunities. For example, this lets it emit this: movq (%rax), %rcx addq %rdx, %rcx instead of this: movq %rdx, %rcx addq (%rax), %rcx in the case where %rdx has subsequent uses. It's the same number of instructions, and usually the same encoding size on x86, but it appears faster, and in general, it may allow better scheduling for the load. llvm-svn: 106493 2010-06-22 00:17:20 +02:00			`; CHECK: mulss`
Turning off post-ra scheduling for x86. It isn't a consistent win. llvm-svn: 98810 2010-03-18 07:55:42 +01:00			`; CHECK: addss`
			`; CHECK: ret`
Added a test case from PR1075. llvm-svn: 33028 2007-01-09 00:58:27 +01:00			`}`