RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-01 08:23:21 +01:00
Code Issues Projects Releases Wiki Activity
df2896d609
llvm-mirror/test/CodeGen/CellSPU/call_indirect.ll

50 lines
2.4 KiB
LLVM
Raw Normal View History

More CellSPU refinement and progress: - Cleaned up custom load/store logic, common code is now shared [see note below], cleaned up address modes - More test cases: various intrinsics, structure element access (load/store test), updated target data strings, indirect function calls. Note: This patch contains a refactoring of the LoadSDNode and StoreSDNode structures: they now share a common base class, LSBaseSDNode, that provides an interface to their common functionality. There is some hackery to access the proper operand depending on the derived class; otherwise, to do a proper job would require finding and rearranging the SDOperands sent to StoreSDNode's constructor. The current refactor errs on the side of being conservatively and backwardly compatible while providing functionality that reduces redundant code for targets where loads and stores are custom-lowered. llvm-svn: 45851
2008-01-11 03:53:15 +01:00
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
More CellSPU refinements: - struct_2.ll: Completely unaligned load/store testing - call_indirect.ll, struct_1.ll: Add test lines to exercise X-form [$reg($reg)] addressing At this point, loads and stores should be under control (he says in an optimistic tone of voice.) llvm-svn: 45882
2008-01-11 22:01:19 +01:00
; RUN: llvm-as -o - %s | llc -march=cellspu -mattr=large_mem > %t2.s
Overhaul Cell SPU's addressing mode internals so that there are now only two addressing mode nodes, SPUaform and SPUindirect (vice the three previous ones, SPUaform, SPUdform and SPUxform). This improves code somewhat because we now avoid using reg+reg addressing when it can be avoided. It also simplifies the address selection logic, which was the main point for doing this. Also, for various global variables that would be loaded using SPU's A-form addressing, prefer D-form offs[reg] addressing, keeping the base in a register if the variable is used more than once. llvm-svn: 46483
2008-01-29 03:16:57 +01:00
; RUN: grep bisl %t1.s | count 7
remove extraneous &&'s from tests, as Scott is apparently not going to. llvm-svn: 46173
2008-01-18 20:53:43 +01:00
; RUN: grep ila %t1.s | count 1
- Remove Tilmann's custom truncate lowering: it completely hosed over DAGcombine's ability to find reasons to remove truncates when they were not needed. Consequently, the CellSPU backend would produce correct, but _really slow and horrible_, code. Replaced with instruction sequences that do the equivalent truncation in SPUInstrInfo.td. - Re-examine how unaligned loads and stores work. Generated unaligned load code has been tested on the CellSPU hardware; see the i32operations.c and i64operations.c in CodeGen/CellSPU/useful-harnesses. (While they may be toy test code, it does prove that some real world code does compile correctly.) - Fix truncating stores in bug 3193 (note: unpack_df.ll will still make llc fault because i64 ult is not yet implemented.) - Added i64 eq and neq for setcc and select/setcc; started new instruction information file for them in SPU64InstrInfo.td. Additional i64 operations should be added to this file and not to SPUInstrInfo.td. llvm-svn: 61447
2008-12-27 05:51:36 +01:00
; RUN: grep rotqby %t1.s | count 6
Overhaul Cell SPU's addressing mode internals so that there are now only two addressing mode nodes, SPUaform and SPUindirect (vice the three previous ones, SPUaform, SPUdform and SPUxform). This improves code somewhat because we now avoid using reg+reg addressing when it can be avoided. It also simplifies the address selection logic, which was the main point for doing this. Also, for various global variables that would be loaded using SPU's A-form addressing, prefer D-form offs[reg] addressing, keeping the base in a register if the variable is used more than once. llvm-svn: 46483
2008-01-29 03:16:57 +01:00
; RUN: grep lqa %t1.s | count 1
CellSPU: Update expected counts on expected patterns llvm-svn: 58927
2008-11-09 02:03:41 +01:00
; RUN: grep lqd %t1.s | count 12
; RUN: grep dispatch_tab %t1.s | count 5
remove extraneous &&'s from tests, as Scott is apparently not going to. llvm-svn: 46173
2008-01-18 20:53:43 +01:00
; RUN: grep bisl %t2.s | count 7
; RUN: grep ilhu %t2.s | count 2
; RUN: grep iohl %t2.s | count 2
; RUN: grep rotqby %t2.s | count 6
CellSPU: - Fix call.ll and call_indirect.ll expected results, now that it's using a different pre-register allocation scheduler. llvm-svn: 60741
2008-12-09 07:12:03 +01:00
; RUN: grep lqd %t2.s | count 13
Fix some tests. The grep for "il" was matching "file". llvm-svn: 60485
2008-12-03 18:14:56 +01:00
; RUN: grep ilhu %t2.s | count 2
CellSPU: Update expected counts on expected patterns llvm-svn: 58927
2008-11-09 02:03:41 +01:00
; RUN: grep ai %t2.s | count 9
; RUN: grep dispatch_tab %t2.s | count 6
More CellSPU refinements: - struct_2.ll: Completely unaligned load/store testing - call_indirect.ll, struct_1.ll: Add test lines to exercise X-form [$reg($reg)] addressing At this point, loads and stores should be under control (he says in an optimistic tone of voice.) llvm-svn: 45882
2008-01-11 22:01:19 +01:00
More CellSPU refinement and progress: - Cleaned up custom load/store logic, common code is now shared [see note below], cleaned up address modes - More test cases: various intrinsics, structure element access (load/store test), updated target data strings, indirect function calls. Note: This patch contains a refactoring of the LoadSDNode and StoreSDNode structures: they now share a common base class, LSBaseSDNode, that provides an interface to their common functionality. There is some hackery to access the proper operand depending on the derived class; otherwise, to do a proper job would require finding and rearranging the SDOperands sent to StoreSDNode's constructor. The current refactor errs on the side of being conservatively and backwardly compatible while providing functionality that reduces redundant code for targets where loads and stores are custom-lowered. llvm-svn: 45851
2008-01-11 03:53:15 +01:00
; ModuleID = 'call_indirect.bc'
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128"
target triple = "spu-unknown-elf"
@dispatch_tab = global [6 x void (i32, float)*] zeroinitializer, align 16
define void @dispatcher(i32 %i_arg, float %f_arg) {
entry:
- Expand tabs to spaces. - select_bits.ll now fully functional now that PR1993 is closed. It was previously broken by refactoring in SPUInstrInfo.td and using multiclasses. - Same for eqv.ll llvm-svn: 47972
2008-03-06 00:00:19 +01:00
%tmp2 = load void (i32, float)** getelementptr ([6 x void (i32, float)*]* @dispatch_tab, i32 0, i32 0), align 16
tail call void %tmp2( i32 %i_arg, float %f_arg )
%tmp2.1 = load void (i32, float)** getelementptr ([6 x void (i32, float)*]* @dispatch_tab, i32 0, i32 1), align 4
tail call void %tmp2.1( i32 %i_arg, float %f_arg )
%tmp2.2 = load void (i32, float)** getelementptr ([6 x void (i32, float)*]* @dispatch_tab, i32 0, i32 2), align 4
tail call void %tmp2.2( i32 %i_arg, float %f_arg )
%tmp2.3 = load void (i32, float)** getelementptr ([6 x void (i32, float)*]* @dispatch_tab, i32 0, i32 3), align 4
tail call void %tmp2.3( i32 %i_arg, float %f_arg )
%tmp2.4 = load void (i32, float)** getelementptr ([6 x void (i32, float)*]* @dispatch_tab, i32 0, i32 4), align 4
tail call void %tmp2.4( i32 %i_arg, float %f_arg )
%tmp2.5 = load void (i32, float)** getelementptr ([6 x void (i32, float)*]* @dispatch_tab, i32 0, i32 5), align 4
tail call void %tmp2.5( i32 %i_arg, float %f_arg )
ret void
More CellSPU refinement and progress: - Cleaned up custom load/store logic, common code is now shared [see note below], cleaned up address modes - More test cases: various intrinsics, structure element access (load/store test), updated target data strings, indirect function calls. Note: This patch contains a refactoring of the LoadSDNode and StoreSDNode structures: they now share a common base class, LSBaseSDNode, that provides an interface to their common functionality. There is some hackery to access the proper operand depending on the derived class; otherwise, to do a proper job would require finding and rearranging the SDOperands sent to StoreSDNode's constructor. The current refactor errs on the side of being conservatively and backwardly compatible while providing functionality that reduces redundant code for targets where loads and stores are custom-lowered. llvm-svn: 45851
2008-01-11 03:53:15 +01:00
}
Forward progress: crtbegin.c now compiles successfully! Fixed CellSPU's A-form (local store) address mode, so that all globals, externals, constant pool and jump table symbols are now wrapped within a SPUISD::AFormAddr pseudo-instruction. This now identifies all local store memory addresses, although it requires a bit of legerdemain during instruction selection to properly select loads to and stores from local store, properly generating "LQA" instructions. Also added mul_ops.ll test harness for exercising integer multiplication. llvm-svn: 46142
2008-01-17 21:38:41 +01:00
@ptr_list = internal global [1 x void ()*] [ void ()* inttoptr (i64 4294967295 to void ()*) ], align 4
@ptr.a = internal global void ()** getelementptr ([1 x void ()*]* @ptr_list, i32 0, i32 1), align 16
define void @double_indirect_call() {
- Expand tabs to spaces. - select_bits.ll now fully functional now that PR1993 is closed. It was previously broken by refactoring in SPUInstrInfo.td and using multiclasses. - Same for eqv.ll llvm-svn: 47972
2008-03-06 00:00:19 +01:00
%a = load void ()*** @ptr.a, align 16
%b = load void ()** %a, align 4
tail call void %b()
ret void
Forward progress: crtbegin.c now compiles successfully! Fixed CellSPU's A-form (local store) address mode, so that all globals, externals, constant pool and jump table symbols are now wrapped within a SPUISD::AFormAddr pseudo-instruction. This now identifies all local store memory addresses, although it requires a bit of legerdemain during instruction selection to properly select loads to and stores from local store, properly generating "LQA" instructions. Also added mul_ops.ll test harness for exercising integer multiplication. llvm-svn: 46142
2008-01-17 21:38:41 +01:00
}
Reference in New Issue Copy Permalink