llvm-mirror/test/CodeGen/XCore/constants.ll

; RUN: llvm-as < %s | llc -march=xcore -mcpu=xs1b-generic | FileCheck %s

; CHECK: .section .cp.rodata.cst4,"aMc",@progbits,4
; CHECK: .LCPI1_0:
; CHECK: .long 12345678
; CHECK: f:
; CHECK: ldw r0, cp[.LCPI1_0]
define i32 @f() {
entry:
	ret i32 12345678
}
Update getSectionForConstant() to to allow mergable sections to be nulled out if not supported by the ELF subtarget. llvm-svn: 79249 2009-08-17 18:37:11 +02:00			`; RUN: llvm-as < %s \| llc -march=xcore -mcpu=xs1b-generic \| FileCheck %s`

Add support for mergeable sections back into the XCore backend. llvm-svn: 79368 2009-08-18 23:14:31 +02:00			`; CHECK: .section .cp.rodata.cst4,"aMc",@progbits,4`
Update getSectionForConstant() to to allow mergable sections to be nulled out if not supported by the ELF subtarget. llvm-svn: 79249 2009-08-17 18:37:11 +02:00			`; CHECK: .LCPI1_0:`
			`; CHECK: .long 12345678`
			`; CHECK: f:`
			`; CHECK: ldw r0, cp[.LCPI1_0]`
			`define i32 @f() {`
			`entry:`
			`ret i32 12345678`
			`}`