RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-30 23:42:52 +01:00
Code Issues Projects Releases Wiki Activity
e096e3c298
llvm-mirror/test/CodeGen/X86/atom-pad-short-functions.ll

104 lines
1.7 KiB
LLVM
Raw Normal View History

Pad Short Functions for Intel Atom The current Intel Atom microarchitecture has a feature whereby when a function returns early then it is slightly faster to execute a sequence of NOP instructions to wait until the return address is ready, as opposed to simply stalling on the ret instruction until the return address is ready. When compiling for X86 Atom only, this patch will run a pass, called "X86PadShortFunction" which will add NOP instructions where less than four cycles elapse between function entry and return. It includes tests. This patch has been updated to address Nadav's review comments - Optimize only at >= O1 and don't do optimization if -Os is set - Stores MachineBasicBlock* instead of BBNum - Uses DenseMap instead of std::map - Fixes placement of braces Patch by Andy Zhang. llvm-svn: 171879
2013-01-08 19:27:24 +01:00
; RUN: llc < %s -O1 -mcpu=atom -mtriple=i686-linux | FileCheck %s
declare void @external_function(...)
define i32 @test_return_val(i32 %a) nounwind {
; CHECK: test_return_val
; CHECK: movl
; CHECK: nop
; CHECK: nop
; CHECK: nop
; CHECK: nop
; CHECK: nop
; CHECK: nop
; CHECK: ret
ret i32 %a
}
define i32 @test_optsize(i32 %a) nounwind optsize {
; CHECK: test_optsize
; CHECK: movl
; CHECK-NEXT: ret
ret i32 %a
}
Update patch for the pad short functions pass for Intel Atom (only). Adds a check for -Oz, changes the code to not re-visit BBs, and skips over DBG_VALUE instrs. Patch by Andy Zhang. llvm-svn: 172258
2013-01-11 23:06:56 +01:00
define i32 @test_minsize(i32 %a) nounwind minsize {
; CHECK: test_minsize
; CHECK: movl
; CHECK-NEXT: ret
ret i32 %a
}
Pad Short Functions for Intel Atom The current Intel Atom microarchitecture has a feature whereby when a function returns early then it is slightly faster to execute a sequence of NOP instructions to wait until the return address is ready, as opposed to simply stalling on the ret instruction until the return address is ready. When compiling for X86 Atom only, this patch will run a pass, called "X86PadShortFunction" which will add NOP instructions where less than four cycles elapse between function entry and return. It includes tests. This patch has been updated to address Nadav's review comments - Optimize only at >= O1 and don't do optimization if -Os is set - Stores MachineBasicBlock* instead of BBNum - Uses DenseMap instead of std::map - Fixes placement of braces Patch by Andy Zhang. llvm-svn: 171879
2013-01-08 19:27:24 +01:00
define i32 @test_add(i32 %a, i32 %b) nounwind {
; CHECK: test_add
; CHECK: addl
; CHECK: nop
; CHECK: nop
; CHECK: nop
; CHECK: nop
; CHECK: ret
%result = add i32 %a, %b
ret i32 %result
}
define i32 @test_multiple_ret(i32 %a, i32 %b, i1 %c) nounwind {
; CHECK: @test_multiple_ret
; CHECK: je
; CHECK: nop
; CHECK: nop
; CHECK: ret
; CHECK: nop
; CHECK: nop
; CHECK: ret
br i1 %c, label %bb1, label %bb2
bb1:
ret i32 %a
bb2:
ret i32 %b
}
define void @test_call_others(i32 %x) nounwind
{
; CHECK: test_call_others
; CHECK: je
%tobool = icmp eq i32 %x, 0
br i1 %tobool, label %if.end, label %true.case
; CHECK: jmp external_function
true.case:
tail call void bitcast (void (...)* @external_function to void ()*)() nounwind
br label %if.end
; CHECK: nop
; CHECK: nop
; CHECK: nop
; CHECK: nop
; CHECK: ret
if.end:
ret void
}
Update patch for the pad short functions pass for Intel Atom (only). Adds a check for -Oz, changes the code to not re-visit BBs, and skips over DBG_VALUE instrs. Patch by Andy Zhang. llvm-svn: 172258
2013-01-11 23:06:56 +01:00
define void @test_branch_to_same_bb(i32 %x, i32 %y) nounwind {
; CHECK: @test_branch_to_same_bb
%cmp = icmp sgt i32 %x, 0
br i1 %cmp, label %while.cond, label %while.end
while.cond:
br label %while.cond
; CHECK: nop
; CHECK: nop
; CHECK: nop
; CHECK: nop
; CHECK: ret
while.end:
ret void
}
Reference in New Issue Copy Permalink