llvm-mirror/test/CodeGen/X86/membarrier.ll

; RUN: llc < %s -march=x86-64 -mattr=-sse -O0
; PR9675

define i32 @t() {
entry:
  %i = alloca i32, align 4
  store i32 1, i32* %i, align 4
  fence seq_cst
  %0 = atomicrmw sub i32* %i, i32 1 monotonic
  fence seq_cst
  ret i32 0
}
Go ahead and emit the barrier on x86-64 even without sse2. The processor supports it just fine. Fixes PR9675 and rdar://9740801 llvm-svn: 134664 2011-07-08 02:04:56 +02:00			`; RUN: llc < %s -march=x86-64 -mattr=-sse -O0`
			`; PR9675`

			`define i32 @t() {`
			`entry:`
			`%i = alloca i32, align 4`
			`store i32 1, i32* %i, align 4`
Last batch of test conversions to new atomic instructions. llvm-svn: 140585 2011-09-27 02:17:29 +02:00			`fence seq_cst`
			`%0 = atomicrmw sub i32* %i, i32 1 monotonic`
			`fence seq_cst`
Go ahead and emit the barrier on x86-64 even without sse2. The processor supports it just fine. Fixes PR9675 and rdar://9740801 llvm-svn: 134664 2011-07-08 02:04:56 +02:00			`ret i32 0`
			`}`