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35 lines
723 B
TableGen
35 lines
723 B
TableGen
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// RUN: llvm-tblgen -gen-emitter -I %p/../../include %s | FileCheck %s
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// Check that EncoderMethod for RegisterOperand is working correctly
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include "llvm/Target/Target.td"
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def ArchInstrInfo : InstrInfo { }
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def Arch : Target {
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let InstructionSet = ArchInstrInfo;
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}
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def Reg : Register<"reg">;
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def RegClass : RegisterClass<"foo", [i32], 0, (add Reg)>;
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def RegOperand : RegisterOperand<RegClass> {
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let EncoderMethod = "barEncoder";
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}
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def foo : Instruction {
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let Size = 1;
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let OutOperandList = (outs);
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let InOperandList = (ins RegOperand:$bar);
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bits<8> bar;
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bits<8> Inst = bar;
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}
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// CHECK: case ::foo: {
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// CHECK: op = barEncoder
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// CHECK: Value |= op & UINT64_C(255);
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// CHECK: break;
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// CHECK: }
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